參數(shù)資料
型號： K4J52324KI-HC1A0
元件分類： DRAM
英文描述： 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝： HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁數(shù)： 46/61頁
文件大?。?/td> 1364K
代理商： K4J52324KI-HC1A0
- 50 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
9. AC & DC OPERATING CONDITIONS
9.1 Absolute Maximem Ratings
NOTE : Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure periods may affect reliability.
9.2 Power & DC Operating Conditions
Recommended operating conditions (Voltage referenced to 0
°C ≤ Tc ≤ 85°C)
NOTE : 1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on
VREF may not exceed + 2 percent of the DC value. Thus, from 70% of VDDQ, VREF is allowed + 25mV for DC error and an additional +25mV
for AC noise.
3. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain
a valid level. The inputs require the AC value to be achieved during signal transition edge and the driver should achieve the same slew rate
through the AC values.
4. Input and output slew rate =3V/ns. If the input slew rate is less than 3V/ns, input timing may be compromised. All slew rate are measured between Vih(AC) and
Vil(AC).
DQ and DM input slew rate must not deviate from DQS by more than 10%. If the DQ,DM and DQS slew rate is less than 3V/ns, timing is longer
than referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points.
5. VIH overshoot: VIH(max) = VDDQ + 0.5V for a pulse width
≤ 500ps and the pulse width can not be greater than 1/3 of the cycle rate.
VIL undershoot: VIL(min)=0.0V for a pulse width
≤ 500ps and the pulse width can not be greater than 1/3 of the cycle rate.
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 ~ VDDQ + 0.5V
V
Voltage on VDD supply relative to Vss
VDD
-0.5 ~ 2.5
V
Voltage on VDDQ supply relative to Vss
VDDQ
-0.5 ~ 2.5
V
MAX Junction Temperature
TJ
+125
°C
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
4
W
Short Circuit Output Current
IOS
50
mA
Parameter
Symbol
Min
Typ
Max
Unit
NOTE
Device Supply voltage
VDD
1.7
1.8
1.9
V1
Output Supply voltage
VDDQ
1.7
1.8
1.9
V
1
Reference voltage
VREF
0.69*VDDQ
-
0.71*VDDQ
V2
DC Input logic high voltage
VIH (DC)
VREF+0.15
--
V
3
DC Input logic low voltage
VIL (DC)
--
VREF-0.15
V3
Output logic low voltage
VOL(DC)
-
0.76
V
AC Input logic high voltage
VIH(AC)
VREF+0.25
-
V
3,4,5
AC Input logic low voltage
VIL(AC)
--
VREF-0.25
V
3,4,5
Input leakage current
Any input 0V-<VIN -< VDDQ
(All other pins not under test = 0V)
II
-5
-
5
uA
Output leakage current
(DQs are disabled; 0V-<VOUT -< VDDQ)
IIOZ
-5
-
5
uA
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