參數(shù)資料
型號: K4J52324KI-HC1A0
元件分類: DRAM
英文描述: 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝: HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁數(shù): 53/61頁
文件大?。?/td> 1364K
代理商: K4J52324KI-HC1A0
- 57 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
[ Table 14 ] AC CHARACTERISTICS - II
Parameter
Symbol
-HC7A(1.3GHz)
-HC08(1.2GHz)
Unit
NOTE
Min
Max
Min
Max
Row active time
tRAS
36
100K
34
100K
tCK
Row cycle time
tRC
51
-
48
-
tCK
Refresh row cycle time
tRFC
66
-
62
-
tCK
RAS to CAS delay for Read
tRCDR
17
-
16
-
tCK
RAS to CAS delay for Write
tRCDW
13
-
12
-
tCK
Row precharge time
tRP
15
-
14
-
tCK
Row active to Row active
tRRD
13
-
12
-
tCK
Last data in to Row precharge (PRE or AutoPRE )
tWR
13
-
13
-
tCK
Last data in to Read command
tCDLR
8
-
8
-
tCK
CAS to CAS command delay
tCCD
BL/2
-
BL/2
-
tCK
Mode register set cycle time
tMRD
10
-
10
-
tCK
Auto precharge write recovery time + Precharge
tDAL
30
-
29
-
tCK
Exit self refresh to Read command
tXSR
20000
-
20000
-
tCK
Exit self refresh to Non-Read command
tXSNR
100
-
100
-
tCK
Power-down exit time
tPDEX
10tCK
+tIS
-
10tCK
+tIS
-tCK
Refresh interval time
tREF
-
3.9
-
3.9
us
CKE minimum pulse width
(High and Low pulse width)
tCKE
5
-
5
-
tCK
Parameter
Symbol
-HC1A(1GHz)
Unit
NOTE
Min
Max
Row active time
tRAS
29
100K
tCK
Row cycle time
tRC
41
-
tCK
Refresh row cycle time
tRFC
52
-
tCK
RAS to CAS delay for Read
tRCDR
14
-
tCK
RAS to CAS delay for Write
tRCDW
10
-
tCK
Row precharge time
tRP
12
-
tCK
Row active to Row active
tRRD
10
-
tCK
Last data in to Row precharge (PRE or Auto-PRE)
tWR
13
-
tCK
Last data in to Read command
tCDLR
7
-
tCK
Mode register set cycle time
tMRD
9
-
tCK
CAS to CAS command delay
tCCD
BL/2
-
tCK
Auto precharge write recovery time + Precharge
tDAL
25
-
tCK
Exit self refresh to Read command
tXSR
20000
-
tCK
Exit self refresh to Non-Read command
tXSNR
100
-
tCK
Power-down exit time
tPDEX
8tCK
+tIS
-tCK
Refresh interval time
tREF
-
3.9
us
CKE minimum pulse width
(High and Low pulse width)
tCKE
5
-
tCK
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