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參數(shù)資料
| 型號： | K4J52324KI-HC1A0 |
| 元件分類： | DRAM |
| 英文描述： | 512M X 1 DDR DRAM, 0.2 ns, PBGA136 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, FBGA-136 |
| 文件頁數(shù)： | 19/61頁 |
| 文件大?。?/td> | 1364K |
| 代理商： | K4J52324KI-HC1A0 |
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K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
AUTO PRECHARGE
Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command.
This is accomplished by using A8 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersis-
tent in that it is either enable or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the ear-
liest valid state within a burst. This "earliest valid stage" is determined as if an explicit PRECHARGE command was issued at the earliest possible time,
without violating tRAS(min), as described for each burst type in the Operation section of this data sheet. The user must not issue another command to the
same bank until the precharge time(tRP) is completed.
AUTO REFRESH
Auto Refresh is used during normal operation of the GDDR3 SGRAM and is analogous to CAS-BEFORE-RAS (CBR) REFRESH in FPM/EDO DRAMs.
This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This
makes the address bits a "Don’t Care" during an Auto Refresh command. The 512Mb(x32) GDDR3 requires Auto Refresh cycles at an average interval of
3.9us (maximum).
A maximum Auto Refresh commands can be posted to any given GDDR3(x32) SGRAM, meaning that the maximum absolute interval between any Auto
Refresh command and the next Auto Refresh command is 9 x 3.9us(35.1us). This maximum absolute interval is to allow GDDR3(x32) SGRAM output
drivers and internal terminators to automatically recalibrate compensating for voltage and temperature changes.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the GDDR3(x32) SGRAM ,even if the rest of the system is powered down. SELF REFRESH
command can be issued only in case all banks are in precharge state. When in the self refresh mode, the GDDR3(x32) SGRAM retains data without
external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automati-
cally disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. The active termination is also dis-
abled upon entering Self Refresh and enabled upon exiting Self Refresh. (20K clock cycles must then occur before a READ command can be issued).
Input signals except CKE are "Don’t Care" during SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK
and CK must be stable prior to CKE going back HIGH. Once CKE is HIGH,the GDDR3(x32) must have NOP commands issued for tXSNR because time
is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh, DLL requirements and out-put calibration is
to apply NOPs for 20K clock cycles before applying any other command to allow the DLL to lock and the output drivers to recalibrate.
* Once the device enters the power down mode, it should be in NOP state at least for 10ns. The minimum duration for the power
down mode once CKE brought to down should be at least 10ns.
Command
CKE
tXSNR
Self
Refresh
~ ~
CK
~ ~
Read
tXSR
Active
tIS
tIH
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| K4J52324QC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
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| K4J52324QC-BC14 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BC14000 | 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC LEAD PART 10W - Trays |
| K4J52324QC-BC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
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