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K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
7.9 Operations
7.9.1 Bank/Row Activation
Figure 8. Example : Meeting tRCD
Before any READ or WRITE commands can be issued to a banks within the GDDR3 SGRAM, a row in that
bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and
the row to be activated.
After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD(min) should be divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after the ACTIVE command in which a READ or WRITE
command can be entered. For example, a tRCD specification of 14ns with a 700MHz clock (1.4ns period)
results in 10 clocks. This is reflected in below figure, which covers any case where 10<tRCD(min)/tCK≤ 11.
The same procedure is used to convert other specification limits from time units to clock cycles).
A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous
active row has been “closed”(precharged). The minimum time interval between successive ACTIVE com-
mands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed,
which results in a reduction of total row access overhead. The minimum time interval between successive
ACTIVE commands to different banks is defined by tRRD.
* Any system or application incorporating random access memory products should be properly designed,
tested and qualified to ensure proper use or access of such memory products. Disproportionate, excessive
and/or repeated access to a particular address or addresses may result in reduction of product life.
CK
RA
CKE
CS
RAS
CAS
WE
A0-A11
BA0,1,2
HIGH
BA
RA = Row Address
BA = Bank Address
Activating a Specific Row
in a Specific Bank
T0
T1
T3
T4
T12
CK
COMMAND
T13
A0-A11
T2
T14
ACT
NOP
ACT
NOP
RD/WR
NOP
Row
Col
BA0~BA2
Bank x
Bank y
tRRD
tRCD
DON’T CARE
CK