參數(shù)資料
型號(hào)： K4J52324KI-HC1A0
元件分類： DRAM
英文描述： 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝： HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁(yè)數(shù)： 30/61頁(yè)
文件大?。?/td> 1364K
代理商： K4J52324KI-HC1A0
- 36 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
NOTE : 1. DO n (or b) = data-out from column n (or column b).
2. Burst length = 4
3. Three subsequent elements of data-out appear in the programmed order following DQ n.
4. Three subsequent elements of data-out appear in the programmed order following DQ b.
5. Shown with nominal tAC and tDQSQ.
6. Example applies when READ commands are issued to different devices or nonconsecutive READs.
7. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
8. The minimum delay from a READ to a PRECHARGE command is BL/2.
Figure 16. READ to PRECHARGE
DON’T CARE
TRANSITIONING DATA
NOP
PRE
NOP
ACT
READ
T0
T1
T2
T8
T8n
T9
T10
CK
COMMAND
ADDRESS
RDQS
DQ
Bank a,
Col n
CL = 8
DO
n
Bank a,
(a or all)
T9n
Bank a,
Row
tRP
BL/2
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K4J52324QC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM
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