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參數(shù)資料
| 型號(hào)： | K4J52324KI-HC1A0 |
| 元件分類： | DRAM |
| 英文描述： | 512M X 1 DDR DRAM, 0.2 ns, PBGA136 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, FBGA-136 |
| 文件頁數(shù)： | 16/61頁 |
| 文件大小： | 1364K |
| 代理商： | K4J52324KI-HC1A0 |
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K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
7.7 Mirror Function
The GDDR3 SGRAM provides a mirror function (MF) ball to change the physical location of the control lines and all address lines which helps to route
devices back to back. The MF ball will affect RAS, CAS, WE, CS and CKE on balls H3, F5, H9, F9 and H4 respectively and A0, A1, A2, A3, A4, A5, A6,
A7, A8, A9, A10, A11, BA0, BA1 and BA2 on balls K4, H2, K3, M4, K9, H11, K10, L9, K11, M9, K2, L4, G4, G9 and H10 respectively and only detects a
DC input. The MF ball should be tied directly to VSS or VDD depending on the control line orientation desired. When the MF ball is tied low the ball orien-
tation is as follows, RAS - H3, CAS - F4, WE - H9, CS - F9, CKE - H4, A0 - K4, A1 - H2, A2 - K3, A3 - M4, A4 - K9, A5 - H11, A6 - K10, A7 - L9, A8 - K11,
A9 - M9, A10 - K2, A11 - L4, BA0 - G4, BA1 - G9 and BA2 - H10. The high condition on the MF ball will change the location of the control balls as follows;
CS - F4, CAS - F9, RAS - H10, WE - H4, CKE - H9, A0 - K9, A1 - H11, A2 - K10, A3 - M9, A4 - K4, A5 - H2, A6 - K3, A7 - L4, A8 - K2, A9 - M4, A10 - K11,
A11 - L9, BA0 - G9, BA1 - G4 and BA2 - H3.
[ Table 7 ] Mirror Function Signal Mapping
PIN
MF LOGIC STATE
HIGH
LOW
RAS
H10
H3
CAS
F9
F4
WE
H4
H9
CS
F4
F9
CKE
H9
H4
A0
K9
K4
A1
H11
H2
A2
K10
K3
A3
M9
M4
A4
K4
K9
A5
H2
H11
A6
K3
K10
A7
L4
L9
A8
K2
K11
A9
M4
M9
A10
K11
K2
A11
L9
L4
BA0
G9
G4
BA1
G4
G9
BA2
H3
H10
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