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參數(shù)資料
| 型號： | K4J52324KI-HC1A0 |
| 元件分類： | DRAM |
| 英文描述： | 512M X 1 DDR DRAM, 0.2 ns, PBGA136 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, FBGA-136 |
| 文件頁數(shù)： | 20/61頁 |
| 文件大?。?/td> | 1364K |
| 代理商： | K4J52324KI-HC1A0 |
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K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
DATA TERMINATOR DISABLE
(BUS SNOOPING FOR READ COMMAND)
The DATA TERMINATOR DISABLE COMMAND is detected by the device by snooping the bus for READ commands excluding /CS. The GDDR3 DRAM
will disable its Data terminators when a READ command is detected. The terminators are disable CL-1 Clocks after the READ command is detected. In a
two rank system both dram devices will snoop the bus for READ commands to either device and both will disable their terminators if a READ command is
detected. The command and address terminators and always enabled.
ON-DIE TERMINATION
Bus snooping for READ commands other than /CS is used to control the on-die termination in the dual load configuration. The GDDR3 SGRAM will dis-
able the on-die termination when a READ command is detected, regardless of the state of
/CS, when the ODT for the DQ pins are set for dual loads (120
Ω). The on-die termination is disabled x clocks after the READ command where x equals
CL-1 and stay off for a duration of BL/2 + 2, as below figure, Data Termination Disable Timing. In a two-rank system, both DRAM devices snoop the bus
for READ commands to either device and both will disable the on-die termination if a READ command is detected. The on-die termination for all other pins
on the device are always on for both a single-rank system and a dual-rank system.
The on-die termination value on address and control pins is determined during power-up in relation to the state of CKE on the first transition of RESET.
On the rising edge of RESET, if CKE is sampled LOW, then the configuration is determined to be a single-rank system. The on-die termination is then set
to one-half ZQ for the address pins. On the rising edge of RESET, if CKE is sampled HIGH, then the configuration is determined to be a dual-rank system.
The on-die termination for the DQs, WDQS, and DM pins is set in the EMRS.
NOTE : 1. DO n = data-out from column n.
2. Burst length = 4.
3. Three subsequent elements of data-out appear in the specified order following DO n.
4. Shown with nominal tAC and tDQSQ.
5. RDQS will start driving high one-half cycle prior to the first falling edge.
6. The Data Terminators are disabled starting at CL-1 and the duration is BL/2 + 2
7. READS to either rank disable both ranks’ termination regardless of the logic level of /CS.
Figure 7. Data Termination Disable Timing
NOP
READ
T0
T7
T8
T8n
T9
T9n
T10
T11
CK
COMMAND
ADDRESS
RDQS
DQ
Bank a,
Col n
CL = 8
DO
n
DQ
TERMINATION
GDDR3 Data Termination is Disabled
DON’T CARE
TRANSITIONING DATA
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