參數(shù)資料
型號: K4J52324KI-HC1A0
元件分類: DRAM
英文描述: 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝: HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁數(shù): 29/61頁
文件大小: 1364K
代理商: K4J52324KI-HC1A0
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K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
NOTE : 1. DO n = data-out from column n.
2. DI b = data-in from column b.
3. Burst length = 4
4. One subsequent element of data-out appears in the programmed order following DO n.
5. Data-in elements are applied following DI b in the programmed order.
6. Shown with nominal tAC and tDQSQ.
7. tDQSS in nominal case.
8. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
9. The gap between data termination enable to the first data-in should be greater than 1tCK
Figure 15. READ to WRITE
DON’T CARE
TRANSITIONING DATA
NOP
WRITE
NOP
READ
T0
T7
T8
T9
T9n
T10
T11
CK
COMMAND
ADDRESS
RDQS
DQ
Bank
Col n
CL = 8
DM
T8n
DO
n
DI
b
tWL = 4
WDQS
DQ
NOP
T12
T12n
Bank a,
Col b
1tCK <
Termination
DQ Termination Disabled
DQ Termination Enabled
CK
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