參數(shù)資料
型號(hào)： ISP1561
廠商： NXP Semiconductors N.V.
英文描述： ISP1561BM
中文描述： ISP1561BM
文件頁數(shù)： 86/102頁
文件大?。?/td> 2875K
代理商： ISP1561
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
86 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6
FPR
Force Port Resume
: A logic 1 means Resume detected or driven on
the port. A logic 0 means no resume (K-state) detected or driven on
the port. Default = 0. Software sets this bit to drive the resume
signaling. The Host Controller sets this bit if a J-to-K transition is
detected while the port is in the suspend state. When this bit changes
to a logic 1 because a J-to-K transition is detected, the PCD (Port
Change Detect) bit in the USBSTS register is also set to a logic 1. If
software sets this bit to a logic 1, the Host Controller must not set the
PCD (Port Change Detect) bit. Note that when the EHCI controller
owns the port, the resume sequence follows the sequence
documented in the USB Specification Rev. 2.0 The resume signaling
(full-speed ‘K’) is driven on the port as long as this bit remains set.
Software must time the Resume and clear this bit after the correct
amount of time has elapsed. Clearing this bit causes the port to return
to high-speed mode (forcing the bus below the port into a high-speed
idle). This bit will remain at one until the port has switched to the
high-speed idle. The Host Controller must complete this transition
within 2 ms of software clearing this bit.
[1]
Overcurrent Change
: Default = 0. This bit is set to a logic 1 when
there is a change in overcurrent active. Software clears this bit by
setting this bit to a one.
Overcurrent Active
: Default = 0. If set to logic 1, this port has an
overcurrent condition. If set to logic 0, this port does not have an
overcurrent condition. This bit will automatically change from a logic 1
to a logic 0 when the overcurrent condition is removed.
Port Enable/Disable Change
: A logic 1 means the Port
enabled/disabled status has changed. A logic 0 means no change.
Default = 0. For the root hub, this bit gets set only when a port is
disabled due to the appropriate conditions existing at the EOF2 point
(See Chapter 11 of the USB Specification Rev. 2.0 for the definition of
a Port Error). Software clears this bit by setting it.
[1]
5
OCC
4
OCA
3
PEDC
Table 117: PORTSC 1, 2, 3, 4 register: bit description
…continued
Bit
Symbol
Description
相關(guān)PDF資料
PDF描述
ISP1561BM ISP1561BM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1561 HI-SPEED USB H 制造商:NXP Semiconductors 功能描述:
ISP1561BM 制造商:NXP Semiconductors 功能描述:
ISP1561BM,518 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BM,551 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BM,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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