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Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
39 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Table 45:
Bit
31 to 11
10
HcControl register: bit description
Symbol
Description
-
reserved
RWE
RemoteWakeupEnable:
This bit is used by the HCD to enable or
disable the remote wake-up feature upon the detection of upstream
resume signaling. When this bit is set and the RD bit in
HcInterruptStatus is set, a remote wake-up is signaled to the host
system. Setting this bit has no impact on the generation of hardware
interrupt.
RWC
RemoteWakeupConnected:
This bit indicates whether the Host
Controller supports remote wake-up signaling. If remote wake-up is
supported and used by the system, it is the responsibility of the
system firmware to set this bit during POST. The Host Controller
clears the bit upon a hardware reset but does not alter it upon a
software reset. Remote wake-up signaling of the host system is
host-bus-specific and is not described in this specification.
InterruptRouting
: This bit determines the routing of interrupts
generated by events registered in HcInterruptStatus. If clear, all
interrupts are routed to the normal host bus interrupt mechanism. If
set, interrupts are routed to the System Management Interrupt. The
HCD clears this bit upon a hardware reset, but it does not alter this
bit upon a software reset. The HCD uses this bit as a tag to indicate
the ownership of the Host Controller.
HCFS[1:0]
HostControllerFunctionalState
for USB:
9
8
7 to 6
00B —
USBRESET
01B —
USBRESUME
10B —
USBOPERATIONAL
11B —
USBSUSPEND
A transition to USBOPERATIONAL from another state causes SOF
generation to begin 1 ms later. The HCD may determine whether the
Host Controller has begun sending SOFs by reading the SF field of
HcInterruptStatus.
This field may be changed by the Host Controller only when in the
USBSUSPEND state. The Host Controller may move from the
USBSUSPEND state to the USBRESUME state after detecting the
resume signaling from a downstream port.
The Host Controller enters USBSUSPEND after a software reset; it
enters USBRESET after a hardware reset. The latter also resets the
Root Hub and asserts subsequent reset signaling to downstream
ports.
BulkListEnable
: This bit is set to enable the processing of the Bulk
list in the next Frame. If cleared by the HCD, processing of the Bulk
list does not occur after the next SOF. The Host Controller checks
this bit whenever it wants to process the list. When disabled, the
HCD may modify the list. If HcBulkCurrentED is pointing to an
Endpoint Descriptor (ED) to be removed, the HCD must advance the
pointer by updating HcBulkCurrentED before re-enabling processing
of the list.
5
BLE