- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360999 > ISP1561 (NXP Semiconductors N.V.) ISP1561BM PDF資料下載
參數(shù)資料
| 型號： | ISP1561 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | ISP1561BM |
| 中文描述： | ISP1561BM |
| 文件頁數(shù)： | 31/102頁 |
| 文件大?。?/td> | 2875K |
| 代理商： | ISP1561 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
31 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Data register (address: value read from address 34H + 7H):
The Data register is
an optional, 1-byte register that provides a mechanism for the function to report state
dependent operating data, such as power consumed or heat dissipation.
Table 40
shows the bit description of the register.
Table 38:
Bit
7
PMCSR_BSE register: bit description
Symbol
Description
BPCC_En
Bus Power/Clock Control Enable
1 —
Indicates that the bus power/clock control mechanism as
defined in
Table 39
is enabled.
0 —
Indicates that the bus/power control policies as defined in
Table 39
have been disabled.
When the Bus Power/Clock Control mechanism is disabled, the
bridge’s PMCSR PS (Power State) field cannot be used by the
system software to control the power or clock of the bridge’s
secondary bus.
6
B2_B3#
B2/B3 support for D3
hot
: The state of this bit determines the
action that is to occur as a direct result of programming the
function to D3
hot
.
1 —
Indicates that when the bridge function is programmed to
D3
hot
, its secondary bus’s PCI clock will be stopped (B2).
0 —
Indicates that when the bridge function is programmed to
D3
hot
, its secondary bus will have its power removed (B3).
This bit is only meaningful if bit 7 (BPCC_En) is logic 1.
reserved
5 to 0
-
Table 39:
Originating device’s bridge PM state
PCI bus power and clock control
Secondary bus PM state
Resultant actions by bridge
(either direct or indirect)
none
none
clock stopped on secondary bus
clock stopped and V
CC
removed from
secondary bus (B3 only). For definition
of B2_B3#, see
Table 38
.
none
D0
D1
D2
D3
hot
B0
B1
B2
B2, B3
D3
cold
B3
Table 40:
Bit
7 to 0
Data register: bit description
Symbol
Access
DATA[7:0]
R
Value
00H
Description
DATA
: This register is used to report the state dependent data
requested by the D_S (Data_Select) field. The value of this register
is scaled by the value reported by the DS (Data_Scale) field.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1561BM | ISP1561BM |
| ISP1562 | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1562BE | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1581 | Universal Serial Bus 2.0 high-speed interface device |
| ISP1581BD | Universal Serial Bus 2.0 high-speed interface device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1561 HI-SPEED USB H | 制造商:NXP Semiconductors 功能描述: |
| ISP1561BM | 制造商:NXP Semiconductors 功能描述: |
| ISP1561BM,518 | 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1561BM,551 | 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1561BM,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。