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| 型號： | ISP1561 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | ISP1561BM |
| 中文描述： | ISP1561BM |
| 文件頁數(shù)： | 34/102頁 |
| 文件大小： | 2875K |
| 代理商： | ISP1561 |
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Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
34 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
B3 state (PCI clock = Stop, PCI bus power = OFF) —
V
DD
has been removed from
all devices on the PCI bus segment.
10.2 USB bus states
Reset state —
When the USB bus is in the reset state, the USB system is stopped.
Operational state —
When the USB bus is in the active state, the USB system is
operating normally.
Suspend state —
When the USB bus is in the suspend state, the USB system is
stopped.
Resume state —
When the USB bus is in the resume state, the USB system is
operating normally.
11. USB Host Controller registers
Each Host Controller contains a set of on-chip operational registers that are mapped
into non-cache memory of system addressable space. This memory space must
begin on a DWord (32-bit) boundary. The size of the allocated space is defined by the
initial value in the BAR 0 register. Host Controller drivers need to interact with these
registers to implement USB and legacy support functionality.
After the PCI enumeration driver finishes the PCI device configuration, the new base
address of these memory-mapped operational registers is defined in BAR 0. The
Host Controller Driver (HCD) can access these registers by using the address of
base address value
+
offset.
Table 41
contains a list of Host Controller registers.
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