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參數(shù)資料
| 型號： | ISP1561 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | ISP1561BM |
| 中文描述： | ISP1561BM |
| 文件頁數(shù)： | 76/102頁 |
| 文件大?。?/td> | 2875K |
| 代理商： | ISP1561 |
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Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
76 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Bit
Symbol
7
6
5
4
3
2
1
0
reserved
IAA
HSE
FLR
PCD
USB
ERRINT
0
R/W
USBINT
Reset
Access
0
-
0
-
0
R
0
0
0
0
R/W
R/W
R/W
R/W
Table 105: USBSTS register: bit description
Bit
Symbol
31 to 16
-
15
ASS
Description
reserved
Asynchronous Schedule Status
: 0 = Default. The bit reports
the current real status of the Asynchronous Schedule. If this bit is
zero, the status of the Asynchronous Schedule is disabled. If this
bit is one, the status of the Asynchronous Schedule is enabled.
The Host Controller is not required to immediately disable or
enable the Asynchronous Schedule when software changes the
ASE (Asynchronous Schedule Enable) bit in the USBCMD
register. When this bit and the ASE (Asynchronous Schedule
Enable) bit are the same value, the Asynchronous Schedule is
either enabled (1) or disabled (0).
Periodic Schedule Status
: 0 = Default. This bit reports the
current status of the Periodic Schedule. If this bit is zero then the
status of the Periodic Schedule is disabled. If this bit is a one
then the status of the Periodic Schedule is enabled. The Host
Controller is not required to immediately disable or enable the
Periodic Schedule when software changes the PSE (Periodic
Schedule Enable) bit in the USBCMD register. When this bit and
the PSE bit are the same value, the Periodic Schedule is either
enabled (1) or disabled (0).
Reclamation
: 0 = Default. This is a read-only status bit that is
used to detect an empty asynchronous schedule.
HCHalted
: 1 = Default. This bit is zero when the Run/Stop bit of
the USBCMD register is one. The Host Controller sets this bit to
one after it has stopped executing as a result of the Run/Stop bit
being set to zero, either by software or by the Host Controller
hardware (for example, on an internal error).
reserved
Interrupt on Asynchronous Advance
: 0 = Default. System
software can force the Host Controller to issue an interrupt the
next time the Host Controller advances the asynchronous
schedule by writing a one to the IAAD (Interrupt on
Asynchronous Advance Doorbell) bit in the USBCMD register.
This status bit indicates the assertion of that interrupt source.
Host System Error
: The Host Controller sets this bit when a
serious error occurs during a host system access involving the
Host Controller module. In a PCI system, conditions that set this
bit include PCI Parity error, PCI Master Abort and PCI Target
Abort. When this error occurs, the Host Controller clears the RS
(Run/Stop) bit in the USBCMD register to prevent further
execution of the scheduled TDs.
14
PSSTAT
13
RECL
12
HCH
11 to 6
5
-
IAA
4
HSE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1561BM | ISP1561BM |
| ISP1562 | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1562BE | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1581 | Universal Serial Bus 2.0 high-speed interface device |
| ISP1581BD | Universal Serial Bus 2.0 high-speed interface device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1561 HI-SPEED USB H | 制造商:NXP Semiconductors 功能描述: |
| ISP1561BM | 制造商:NXP Semiconductors 功能描述: |
| ISP1561BM,518 | 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1561BM,551 | 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1561BM,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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