參數(shù)資料
型號(hào)： ISP1561
廠商： NXP Semiconductors N.V.
英文描述： ISP1561BM
中文描述： ISP1561BM
文件頁數(shù)： 19/102頁
文件大小： 2875K
代理商： ISP1561
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
19 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Table 9:
Bit
15
Status register: bit description
Symbol
DPE
Description
Detected Parity Error
: This bit must be set by the device
whenever it detects a parity error, even if the parity error
handling is disabled.
Signaled System Error
: This bit must be set whenever the
device asserts SERR#. Devices that never assert SERR# do not
need to implement this bit.
Received Master Abort
: This bit must be set by a master
device whenever its transaction (except for Special Cycle) is
terminated with Master-Abort. All master devices must
implement this bit.
Received Target Abort
: This bit must be set by a master device
whenever its transaction is terminated with Target-Abort. All
master devices must implement this bit.
Signaled Target Abort
: This bit must be set by a target device
whenever it terminates a transaction with Target-Abort. Devices
that never signal Target-Abort do not need to implement this bit.
DEVSEL Timing
: These bits encode the timing of DEVSEL#.
There are three allowable timings for assertion of DEVSEL#:
14
SSE
13
RMA
12
RTA
11
STA
10 to 9
DEVSELT[1:0]
00B —
for fast
01B —
for medium
10B —
for slow
11B —
is reserved
These bits are read-only and must indicate the slowest time that
a device asserts DEVSEL# for any bus command except
Configuration Read and Configuration Write.
Master Data Parity Error:
This bit is implemented by bus
masters. It is set when the following three conditions are met:
The bus agent asserted PERR# itself (on a read) or observed
PERR# asserted (on a write).
The agent setting the bit acted as the bus master for the
operation in which error occurred.
The Parity Error Response bit (in the Command register) is
set.
Fast Back-to-Back Capable
: This read-only bit indicates
whether or not the target is capable of accepting fast
back-to-back transactions when the transactions are not to the
same agent. This bit can be set to logic 1 if the device can
accept these transactions and must be set to logic 0 otherwise.
reserved
8
MDPE
7
FBBC
6
-
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1561 HI-SPEED USB H 制造商:NXP Semiconductors 功能描述:
ISP1561BM 制造商:NXP Semiconductors 功能描述:
ISP1561BM,518 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BM,551 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BM,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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