參數(shù)資料
型號： ISP1561
廠商： NXP Semiconductors N.V.
英文描述： ISP1561BM
中文描述： ISP1561BM
文件頁數(shù)： 75/102頁
文件大?。?/td> 2875K
代理商： ISP1561
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
75 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.4.2
USBSTS register (address: value read from func2 of address 10H + 10H)
The USB Status (USBSTS) register indicates pending interrupts and various states of
the Host Controller. The status resulting from a transaction on the serial bus is not
indicated in this register. Software clears the register bits by writing ones to them. The
bit allocation is given in
Table 104
.
1
HCRESET
Host Controller Reset
: This control bit is used by the software to
reset the Host Controller. The effects of this on Root Hub registers are
similar to a Chip Hardware Reset. Setting this bit causes the Host
Controller to reset its internal pipelines, timers, counters, state
machines, etc. to their initial value. Any transaction currently in
progress on USB is immediately terminated. A USB reset is not driven
on downstream ports. PCI Configuration registers are not affected by
this reset. All operational registers, including port registers and port
state machines are set to their initial values. Port ownership reverts to
the companion Host Controller(s). The software must re-initialize the
Host Controller to return it to an operational state. This bit is cleared
by the Host Controller when the reset process is complete. Software
cannot terminate the reset process early by writing a zero to this
register. Software should check the HCH (HCHalted) bit in the
USBSTS register is zero before setting this bit. Attempting to reset an
actively running Host Controller results in undefined behavior.
RS
Run/Stop
: 1 = Run. 0 = Stop. When set, the Host Controller executes
the schedule. The Host Controller continues execution as long as this
bit is set. When this bit is cleared, the Host Controller completes the
current and active transactions in the USB pipeline, and then halts.
The HCH (HCHalted) bit in the USBSTS register indicates when the
Host Controller has finished the transaction and has entered the
stopped state. Software should check HCH (HCHalted) in the
USBSTS register is logic 1 before setting this bit.
0
Table 103: USBCMD register: bit description
…continued
Bit
Symbol
Description
Table 104: USBSTS register: bit allocation
Bit
31
Symbol
Reset
0
Access
-
Bit
23
Symbol
Reset
0
Access
-
Bit
15
Symbol
ASS
Reset
0
Access
R
30
29
28
27
26
25
24
reserved
0
-
0
-
0
-
0
-
0
-
0
-
0
-
22
21
20
19
18
17
16
reserved
0
-
0
-
0
-
0
-
0
-
0
-
9
0
-
8
14
13
12
HCH
1
R
11
10
PSSTAT
0
R
RECL
0
R
reserved
0
-
0
-
0
-
0
-
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1561 HI-SPEED USB H 制造商:NXP Semiconductors 功能描述:
ISP1561BM 制造商:NXP Semiconductors 功能描述:
ISP1561BM,518 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BM,551 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BM,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
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