參數(shù)資料
型號： ISP1561
廠商： NXP Semiconductors N.V.
英文描述： ISP1561BM
中文描述： ISP1561BM
文件頁數(shù)： 77/102頁
文件大?。?/td> 2875K
代理商： ISP1561
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
77 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.4.3
USBINTR register (address: value read from func2 of address 10H + 14H)
The USB Interrupt Enable (USBINTR) register enables and disables reporting of the
corresponding interrupt to the software. When a bit is set and the corresponding
interrupt is active, an interrupt is generated to the host. Interrupt sources that are
disabled in this register still appear in the USBSTS to allow the software to poll for
events. The USBSTS register bit allocation is give in
Table 106
.
3
FLR
Frame List Rollover
: The Host Controller sets this bit to a one
when the Frame List Index rolls over from its maximum value to
zero. The exact value at which the rollover occurs depends on
the frame list size. For example, if the frame list size (as
programmed in the FLS (Frame List Size) field of the USBCMD
register) is 1024, the Frame Index Register rolls over every time
bit 13 of the FRINDEX register toggles. Similarly, if the size is
512, the Host Controller sets this bit to a one every time bit 12 of
the FRINDEX register toggles.
Port Change Detect
: The Host Controller sets this bit to a one
when any port, where the PO (Port Owner) bit is cleared, has a
change to a one or a Force Port Resume bit changes to a one as
a result of a J-K transition detected on a suspended port. This bit
is allowed to be maintained in the Auxiliary power well.
Alternatively, it is also acceptable that, on a D3 to D0 transition of
the EHCI HC device, this bit is loaded with the logical OR of all of
the PORTSC change bits (including: Force port resume,
overcurrent change, enable/disable change and connect status
change).
USB Error Interrupt
: The Host Controller sets this bit when
completion of a USB transaction results in an error condition (for
example, error counter underflow). If the TD (Transfer Descriptor)
on which the error interrupt occurred also had its IOC bit set,
both this bit and USBINT bit are set.
USB Interrupt
: The Host Controller sets this bit on completion of
a USB transaction, which results in the retirement of a Transfer
Descriptor that had its IOC bit set. The Host Controller also sets
this bit when a short packet is detected (actual number of bytes
received was less than the expected number of bytes).
2
PCD
1
USBERRINT
0
USBINT
Table 105: USBSTS register: bit description
…continued
Bit
Symbol
Description
Table 106: USBINTR register: bit allocation
Bit
31
Symbol
Reset
0
Access
-
Bit
23
Symbol
Reset
0
Access
-
30
29
28
27
26
25
24
reserved
0
-
0
-
0
-
0
-
0
-
0
-
0
-
22
21
20
19
18
17
16
reserved
0
-
0
-
0
-
0
-
0
-
0
-
0
-
相關(guān)PDF資料
PDF描述
ISP1561BM ISP1561BM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1561 HI-SPEED USB H 制造商:NXP Semiconductors 功能描述:
ISP1561BM 制造商:NXP Semiconductors 功能描述:
ISP1561BM,518 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BM,551 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BM,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
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