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參數資料
| 型號： | ISP1561 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | ISP1561BM |
| 中文描述： | ISP1561BM |
| 文件頁數： | 21/102頁 |
| 文件大小： | 2875K |
| 代理商： | ISP1561 |
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Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
21 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
CacheLine Size register (address: 0CH):
The CacheLine Size register is a
read/write single byte register that specifies the system cacheline size in units of
DWords. This register must be implemented by master devices that can generate the
Memory Write and Invalidate command. The value in this register is also used by
master devices to determine whether to use Read, Read Line, or Read Multiple
commands for accessing memory.
Slave devices that want to allow memory bursting using a cacheline-wrap addressing
mode must implement this register to know when a burst sequence wraps to the
beginning of the cacheline.
This field must be initialized to logic 0 on activation of RST#.
Table 13
shows the bit
description of the CacheLine Size register.
Latency Timer register (address: 0DH):
This one-byte register specifies, in units of
PCI bus clocks, the value of the Latency Timer for the PCI bus master. The Latency
Time register bit description is given in
Table 14
.
This register must be implemented as writable by any master that can burst more
than two data phases. This register may be implemented as read-only for devices that
burst two or fewer data phases, but the fixed value must be limited to 16 or less. The
register must be initialized to logic 0 at RST#, if programmable.
Header Type register (address: 0EH):
The Header Type register identifies the
layout of the second part of the predefined header (beginning at byte 10H in
Configuration Space). It also identifies whether or not the device contains multiple
functions (bit allocation: see
Table 15
).
Table 12:
Bit
23 to 16
Class Code register: bit description
Symbol
Description
BCC[7:0]
Base Class Code
: 0CH is the base class code assigned to this
byte, and it implies a serial bus controller.
SCC[7:0]
Sub-Class Code
: 03H is the sub-class code assigned to this byte,
and it implies the USB Host Controller.
RLPI[7:0]
Register-Level Programming Interface
: 10H is the programming
interface code assigned to OHCI, which is USB 1.1 specification
compliant. 20H is the programming interface code assigned to
EHCI, which is USB 2.0 specification compliant.
15 to 8
7 to 0
Table 13:
Bit
7 to 0
CacheLine Size register: bit description
Symbol
Access
CLS[7:0]
R/W
Value
00H
Description
CacheLine Size
: This byte identifies the system cacheline size.
Table 14:
Bit
7 to 0
Latency Timer register: bit description
Symbol
Access
LT[7:0]
R/W
Value
00H
Description
Latency Timer
: This byte identifies the latency timer.
Table 15:
Bit
Symbol
Reset
Access
Header Type register: bit allocation
7
MFD
1
R
6
5
4
3
2
1
0
HT[6:0]
0
R
0
R
0
R
0
R
0
R
0
R
0
R
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1561BM | ISP1561BM |
| ISP1562 | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1562BE | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1581 | Universal Serial Bus 2.0 high-speed interface device |
| ISP1581BD | Universal Serial Bus 2.0 high-speed interface device |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1561 HI-SPEED USB H | 制造商:NXP Semiconductors 功能描述: |
| ISP1561BM | 制造商:NXP Semiconductors 功能描述: |
| ISP1561BM,518 | 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1561BM,551 | 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1561BM,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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