參數(shù)資料
型號(hào)： ISP1561
廠商： NXP Semiconductors N.V.
英文描述： ISP1561BM
中文描述： ISP1561BM
文件頁(yè)數(shù)： 74/102頁(yè)
文件大?。?/td> 2875K
代理商： ISP1561
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
74 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
15 to 8
7
-
LHCR
reserved
Light Host Controller Reset
: This control bit is not required. It allows
the driver software to reset the EHCI controller without affecting the
state of the ports or the relationship to the companion Host
Controllers. If not implemented, a read of this field will always return
zero.If implemented, on read:
logic 0 —
indicates the Light Host Controller Reset has completed
and it is ready for the host software to re-initialize the Host Controller
logic 1 —
indicates the Light Host Controller Reset has not yet
completed
Interrupt on Asynchronous Advance Doorbell
: This bit is used as a
doorbell by software to tell the Host Controller to issue an interrupt the
next time it advances the asynchronous schedule. Software must
write logic 1 to this bit to ring the doorbell. When the Host Controller
has evicted all appropriate cached schedule states, it sets the IAA
(Interrupt on Asynchronous Advance) status bit in the USBSTS
register. If the IAAE (Interrupt on Asynchronous Advance Enable) bit
in the USBINTR register is a one, then the Host Controller will assert
an interrupt at the next interrupt threshold. The Host Controller sets
this bit to a zero after it sets the IAA (Interrupt on Asynchronous
Advance) status bit in the USBSTS register. Software should not set
this bit when the asynchronous schedule is inactive as this results in
an undefined value.
Asynchronous Schedule Enable
: Default = 0. This bit controls
whether the Host Controller skips processing the Asynchronous
Schedule.
6
IAAD
5
ASE
logic 0 —
Do not process the Asynchronous Schedule
logic 1 —
Use the ASYNCLISTADDR register to access the
Asynchronous Schedule
Periodic Schedule Enable
: Default 0. This bit controls whether the
Host Controller skips processing the Periodic Schedule.
4
PSE
logic 0 —
Do not process the Periodic Schedule
logic 1 —
Use the PERIODICLISTBASE register to access the
Periodic Schedule
Frame List Size
: Default 00B. This field is R/W only if PFLF
(Programmable Frame List Flag) in the HCCPARAMS register is set to
a one. This field specifies the size of the frame list. The size the frame
list controls which bits in the Frame Index register should be used for
the Frame List Current index.
3 to 2
FLS[1:0]
00B —
1024 elements (4096 bytes)
01B —
512 elements (2048 bytes)
10B —
256 elements (1024 bytes) for small environments
11B —
reserved.
Table 103: USBCMD register: bit description
…continued
Bit
Symbol
Description
相關(guān)PDF資料
PDF描述
ISP1561BM ISP1561BM
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ISP1562BE Hi-Speed Universal Serial Bus PCI Host Controller
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ISP1581BD Universal Serial Bus 2.0 high-speed interface device
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1561 HI-SPEED USB H 制造商:NXP Semiconductors 功能描述:
ISP1561BM 制造商:NXP Semiconductors 功能描述:
ISP1561BM,518 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BM,551 功能描述:USB 接口集成電路 USB 2.0 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1561BM,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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