參數(shù)資料
型號(hào): ISP1362EE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù): 94/150頁
文件大?。?/td> 647K
代理商: ISP1362EE
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
94 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15.4.2
HcDMACon
fi
guration register (R/W: 21H/A1H)
Table 65
contains the bit allocation of the HcDMACon
fi
guration register.
Code (Hex): 21
read
Code (Hex): A1
write
Table 65:
Bit
Symbol
Reset
Access
Bit
Symbol
HcDMACon
fi
guration register: bit allocation
15
14
13
12
11
10
9
8
reserved
-
-
7
-
-
6
-
-
5
-
-
4
-
-
3
-
-
2
-
-
1
-
-
0
DMACounter
Enable
0
R/W
BurstLen[1:0]
DMA
Enable
0
R/W
Buffer_Type_Select[2:0]
DMARead
WriteSelect
0
R/W
Reset
Access
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Table 66:
Bit
15 to 8
7
HcDMACon
fi
guration register: bit description
Symbol
-
DMACounterEnable
Description
reserved
0
reserved
1
DMA counter is enabled. Once the counter is
enabled, the HCD must initialize the HcTransferCounter
register to a non-zero value for DREQ to be raised after
the DMAEnable bit is set to HIGH.
00
single-cycle burst DMA
6 to 5
BurstLen[1:0]
01
4-cycle burst DMA
10
8-cycle burst DMA
11
reserved
I/O bus with 32-bit data path width supports only single
and four cycle DMA burst.
0
DMA is disabled
4
DMAEnable
1
DMA is enabled
This bit needs to be reset when the DMA transfer is
completed.
Bit 3
Bit 2
Bit 1
Buffer Type
0
0
0
ISTL0 (default)
0
0
1
ISTL1
0
1
0
INTL
0
1
1
ATL
1
X
X
Direct Addressing
0
read from the buffer memory of the HC
3 to 1
Buffer_Type_Select
[2:0]
0
DMAReadWriteSelect
1
write to the buffer memory of the HC
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