參數(shù)資料
型號(hào)： ISP1362EE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Single-chip Universal Serial Bus On-The-Go controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 121/150頁
文件大小： 647K
代理商： ISP1362EE
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
—
06 January 2004
121 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
16.2.3
Stall Endpoint or Unstall Endpoint (40H
–
4FH/80H
–
8FH)
These commands are used to stall or unstall an endpoint. The commands modify the
content of the DcEndpointStatus register (see
Table 124
).
A stalled control endpoint is automatically unstalled when it receives a SET-UP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microprocessor can re-stall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by using the Unstall Endpoint command
or by receiving a SET-UP token), it is also re-initialized. This
fl
ushes the buffer: if it is
an OUT buffer, it waits for a DATA 0 PID; if it is an IN buffer, it writes a DATA 0 PID.
Code (Hex): 40 to 4F
—
stall (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 80 to 8F
—
unstall (control OUT, control IN, endpoint 1 to 14)
Transaction
—
none (code only)
Table 124: DcEndpointStatus register: bit allocation
Bit
7
Symbol
EPSTAL
6
5
4
3
2
1
0
EPFULL1
EPFULL0
DATA_PID
OVER
WRITE
0
R
SETUPT
CPUBUF
reserved
Reset
Access
0
R
0
R
0
R
0
R
0
R
0
R
-
-
Table 125: DcEndpointStatus register: bit description
Bit
Symbol
7
EPSTAL
Description
This bit indicates whether the endpoint is stalled or not
(1 = stalled; 0 = not stalled).
Set to logic 1 by a Stall Endpoint command, cleared to logic 0 by
an Unstall Endpoint command. The endpoint is automatically
unstalled on receiving a SET-UP token.
Logic 1 indicates that the secondary endpoint buffer is full.
Logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the next packet (0 = DATA PID;
1 = DATA1 PID).
This bit is set by hardware. Logic 1 indicates that a new Set-up
packet has overwritten the previous set-up information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the set-up data has
fi
nished.
Firmware must check this bit before sending an Acknowledge
Set-up command or stalling the endpoint. Upon reading logic 1,
the
fi
rmware must stop ongoing set-up actions and wait for a
new Set-up packet.
Logic 1 indicates that the buffer contains a Set-up packet.
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer; 1 = secondary buffer).
reserved
6
5
4
EPFULL1
EPFULL0
DATA_PID
3
OVERWRITE
2
1
SETUPT
CPUBUF
0
-
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