參數(shù)資料
型號: ISP1362EE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù): 10/150頁
文件大小: 647K
代理商: ISP1362EE
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
10 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
V
CC
26
J7
-
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01
μ
F
digital ground
DMA acknowledge input; indicates that a request for DMA transfer
from the HC has been granted by the DMA controller; the active level
(HIGH or LOW) of the acknowledge signal is programmed by using the
HcHardwareCon
fi
guration register (20H/A0H); when not in use, this
pin must be connected to V
CC
through a 10 k
resistor
input with hysteresis
DMA acknowledge input; indicates that a request for DMA transfer
from the DC has been granted by the DMA controller; the active level
(HIGH or LOW) of the acknowledge signal is programmed by using the
DcHardwareCon
fi
guration register (BAH/BBH); when not in use, this
pin must be connected to V
CC
through a 10 k
resistor
input with hysteresis
interrupt request from the HC; provides a mechanism for the HC to
interrupt the microprocessor; see HcHardwareCon
fi
guration register
(20H/A0H)
Section 15.4.1
for details
If the OneINT bit of the HcHardwareCon
fi
guration register is set to
logic 1, both the HC and DC interrupt request will be routed to INT1.
push-pull output
interrupt request from the DC; provides a mechanism for the DC to
interrupt the microprocessor; see DcHardwareCon
fi
guration register
(BAH/BBH)
Section 16.1.4
for details
push-pull output
reset input
input with hysteresis and internal pull-up resistor
I/O pin (open-drain); goes HIGH when the HC is in the
suspend
mode; a LOW pulse must be applied to this pin to wake up the HC;
connect a 100 k
resistor to V
CC
bidirectional, push-pull input, three-state open-drain output
I/O pin (open-drain); goes HIGH when the DC is in the
suspend
mode; a LOW pulse must be applied to this pin to wake up the DC;
connect a 100 k
resistor to V
CC
bidirectional, push-pull input, three-state open-drain output
connects to the external PMOS switch; required when the external
charge pump or external V
BUS
is used for providing V
BUS
to the
downstream port
DGND
DACK1
27
28
K7
J8
-
I
DACK2
29
K8
I
INT1
30
J9
O
INT2
31
K9
O
RESET
32
K10
I
H_SUSPEND/
H_WAKEUP
33
J10
I/O
D_SUSPEND/
D_WAKEUP
34
H9
I/O
H_PSW1
35
H10
O
LOW
switches ON the PMOS providing V
BUS
to the downstream
port
HIGH
switches OFF the PMOS
when not in use, leave this pin open
open-drain output
Table 2:
Symbol
[1]
Pin description
continued
Pin
LQFP64
Ball
TFBGA64
Type
[2]
Description
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