參數(shù)資料
型號: ISP1362EE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù): 46/150頁
文件大小: 647K
代理商: ISP1362EE
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
46 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ATL buffer is now ready for processing. Once the ATL_Active bit of the HcBufferStatus
register is set, the USB packet is sent out. The active bit in the PTD is cleared once
the PTD is sent. Depending on the outcome of the USB transfer, the 4-bit completion
code is updated.
12.6 Features of the interrupt transfer
An interrupt transaction is sent out periodically, according to the
interrupt polling
rate
as de
fi
ned in the PTD.
An interrupt transaction causes an interrupt to the CPU only if the transaction is
ACKed or has error conditions, such as STALL or no respond. An ACK condition
occurs if data is received on the IN token or data is sent out on the OUT token.
An interrupt is activated only once every ms as long as there is ACK for different
interrupt transactions in the interrupt transfer buffer.
Each interrupt transfer (PTD) placed in the INTL buffer can automatically hold or
send data for more than 1 ms. This can be done using the parameters in the PTD.
12.7 Features of the isochronous (ISO) transfer
Supports multi-buffering by using the ISTL0 or ISTL1 toggling mechanism.
The CPU can decide (in ms) how fast it can serve the ISP1362. This gives the
CPU the
fl
exibility to decide how much time it takes to read and
fi
ll in the ISO data.
The ISTL buffer can be updated on-the-
fl
y by using the direct addressing memory
architecture.
12.8 Overcurrent protection circuit
The ISP1362 has a built-in overcurrent protection circuitry. You can enable or disable
this feature by setting or resetting AnalogOCEnable (bit 10) of the
HcHardwareCon
fi
guration register. If this feature is disabled, it is assumed that there
is an external overcurrent protection circuitry.
Table 13:
N bits [7:5]
0
1
2
3
4
5
6
7
Interrupt polling
StartingFrame N[4:0]
Frame 0 to 31
Frame 0 to 31
Frame 0 to 31
Frame 0 to 31
Frame 0 to 31
Frame 0 to 31
Frame 0 to 31
Frame 0 to 31
Interrupt polling interval (2
N
) in ms
1
2
4
8
16
32
64
128
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