參數(shù)資料
型號: ISP1362EE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù): 66/150頁
文件大?。?/td> 647K
代理商: ISP1362EE
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
66 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
14.4 OtgInterruptEnable register (R/W: 69H/E9H)
Code (Hex): 69
read
Code (Hex): E9
write
Table 28:
Bit
Symbol
OtgInterruptEnable register: bit allocation
15
14
13
12
11
10
9
8
reserved
OTG_
TMR_IE
0
R/W
2
B_SESS_
END_IE
B_SE0_
SRP_IE
0
R/W
1
A_VBUS_
VLD_IE
A_SRP_
DET_IE
0
R/W
0
ID_REG_
IE
Reset
Access
Bit
Symbol
-
-
7
-
-
6
-
-
5
-
-
4
-
-
3
OTG_
RESUME_
IE
0
R/W
OTG_
SUSPND_
IE
0
R/W
RMT_
CONN_IE
B_SESS_
VLD_IE
A_SESS_
VLD_IE
Reset
Access
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 29:
Bit
15 to 11
10
OtgInterruptEnable register: bit description
Symbol
Description
-
reserved
OTG_
TMR_IE
B_SE0_
SRP_IE
change.
A_SRP_
DET_IE
OTG_
RESUME_
IE
OTG_
SUSPND_
IE
RMT_
CONN_IE
change.
B_SESS_
VLD_IE
change.
A_SESS_
VLD_IE
change.
B_SESS_
END_IE
change.
A_VBUS_
VLD_IE
change.
ID_REG_IE Logic 1 enables interrupt upon detection of the ID_REG status
change.
Logic 1 enables interrupt when the OTG timer attains time-out.
9
Logic 1 enables interrupt upon detection of the B_SE0_SRP status
8
Logic 1 enables interrupt upon detection of the SRP event.
7
Logic 1 enables interrupt upon detection of bus resume (J to K
only) event.
6
Logic 1 enables interrupt upon detection of the bus
suspend
status change.
5
Logic 1 enables interrupt upon detection of the RMT_CONN status
4
Logic 1 enables interrupt upon detection of B_SESS_VLD status
3
Logic 1 enables interrupt upon detection of A_SESS_VLD status
2
Logic 1 enables interrupt upon detection of B_SESS_END status
1
Logic 1 enables interrupt upon detection of A_VBUS_VLD status
0
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