參數(shù)資料
型號: ISP1362EE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù): 77/150頁
文件大?。?/td> 647K
代理商: ISP1362EE
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
77 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
writing logic 0 to a bit in this register leaves the corresponding bit in the
HcInterruptEnable register unchanged. On a read, the current value of the
HcInterruptEnable register is returned.
Table 45
provides the bit allocation of the
HcInterruptDisable register.
Code (Hex): 05
read
Code (Hex): 85
write
Table 45:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptDisable register: bit allocation
31
30
MIE
0
-
R/W
-
23
22
29
28
27
26
25
24
reserved
-
-
19
-
-
-
-
-
-
-
-
-
-
21
20
18
17
16
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9
-
-
8
15
14
13
12
11
10
reserved
-
-
7
-
-
6
-
-
5
-
-
4
-
-
3
-
-
2
-
-
1
-
-
0
reserved
-
-
RHSC
0
R/W
FNO
0
R/W
UE
0
R/W
RD
0
R/W
SF
0
R/W
reserved
-
-
SO
0
R/W
Table 46:
Bit
31
HcInterruptDisable register: bit description
Symbol
Description
MIE
Logic 0 is ignored by the HC. Logic 1 disables interrupt generation
because of events speci
fi
ed in other bits of this register. This
fi
eld
is set after a hardware or software reset.
-
reserved
RHSC
0
ignore
30 to 7
6
1
disable interrupt generation because of Root Hub Status
Change
0
ignore
5
FNO
1
disable interrupt generation because of Frame Number
Over
fl
ow
0
ignore
4
UE
1
disable interrupt generation because of Unrecoverable Error
0
ignore
3
RD
1
disable interrupt generation because of Resume Detect
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