參數(shù)資料
型號(hào): ISP1362EE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁(yè)數(shù): 104/150頁(yè)
文件大?。?/td> 647K
代理商: ISP1362EE
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Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
104 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The HCD is
fi
rst required to initialize the HcTransferCounter register with the byte
count to be transferred and check the HcBufferStatus register. The HCD then sends
the command (43H for reading of the INTL buffer, and C3H for writing to the INTL
buffer) to the HC through the I/O port of the microprocessor. After the command is
sent, the HCD starts reading data from the INTL buffer or writing data to the INTL
buffer. While the HCD is accessing the buffer, the buffer pointer of INTL also
increases automatically. When the pointer has reached the initialized byte count of
the HcTransferCounter register, the HC sets the AllEOTInterrupt bit of the
Hc
μ
PInterrupt register to logic 1 and updates the HcBufferStatus register.
15.8.3
HcINTLBlkSize register (R/W: 53H/D3H)
The ISP1362 requires the INTL buffer to be partitioned into several equal sized blocks
so that the HC can skip the current PTD and proceed to process the next PTD easily.
The block size of the INTL buffer is required to be speci
fi
ed in this register and must
be a multiple of 8 bytes. The default value of the block size is 64 bytes, and the
maximum allowable block size is 1024 bytes.
Table 87
shows the bit allocation of the
register.
Code (Hex): 53
read
Code (Hex): D3
write
15.8.4
HcINTLPTDDoneMap register (R: 17H)
This is a 32-bit register, and the bit description is given in
Table 89
. Every bit of the
register represents the processing status of a PTD. Bit 0 of the register represents the
fi
rst PTD stored in the INTL buffer, bit 1 represents the second PTD stored in the
buffer, and so on. The register is updated once every ms by the HC and is cleared
upon read by the HCD. Bits that are set representing its corresponding PTDs are
processed by the HC and the ACK token is received from the device.
Code (Hex): 17
read only
Table 87:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcINTLBlkSize register: bit allocation
15
14
13
12
11
10
9
BlockSize[9:8]
0
R/W
1
8
reserved
-
-
7
-
-
6
-
-
5
-
-
4
BlockSize[7:0]
0
R/W
-
-
3
-
-
2
0
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 88:
Bit
15 to 10
9 to 0
HcINTLBlkSize register: bit description
Symbol
Description
-
reserved
BlockSize[9:0]
The block size of the INTL buffer.
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