參數(shù)資料
型號： ISP1362EE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Single-chip Universal Serial Bus On-The-Go controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 33/150頁
文件大?。?/td> 647K
代理商： ISP1362EE
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
—
06 January 2004
33 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
communicates with the A-device as long as it wishes. When the B-device
fi
nishes
communicating with the A-device, both the devices
fi
nally go into the idle state. See
Figure 18
and
Figure 19
.
11.3 Session Request Protocol (SRP)
As a dual-role device, the ISP1362 can initiate and respond to SRP. The B-device
initiates SRP by data line pulsing followed by V
BUS
pulsing. The A-device can detect
either data line pulsing or V
BUS
pulsing.
11.3.1
B-device initiating SRP
The ISP1362 can initiate SRP by performing the following steps:
1. Detect initial conditions [read ID_REG, B_SESS_END and SE0_2MS (bits 0,
2 and 9) of the OtgStatus register].
2. Start data line pulsing [set LOC_CONN (bit 4) of OtgControl register to logic 1].
3. Wait for 5 ms to 10 ms.
4. Stop data line pulsing [set LOC_CONN (bit 4) of OtgControl register to logic 0].
5. Start V
BUS
pulsing [set CHRG_V
BUS
(bit 1) of the OtgControl register to logic 1].
6. Wait for 10 ms to 20 ms.
7. Stop V
BUS
pulsing [set CHRG_V
BUS
(bit 1) of the OtgControl register to logic 0].
8. Discharge V
BUS
for about 30 ms [by using DISCHRG_V
BUS
(bit 2) of the
OtgControl register], optional.
The B-device must complete both data line pulsing and V
BUS
pulsing within 100 ms.
11.3.2
A-device responding to SRP
The A-device must be able to respond to one of the two SRP events: data line pulsing
or V
BUS
pulsing. The ISP1362 allows you to choose which SRP to support and has a
mechanism to disable or enable the SRP detection. This is useful for some
applications under certain cases. For example, if the A-device battery is low, it may
not want to turn on its V
BUS
by detecting SRP. In this case, it may choose to disable
the SRP detection function.
When the data line SRP detection is used, the ISP1362 can detect either the
DP pulsing or the DM pulsing. This means a peripheral-only device can initiate data
line pulsing SRP through DP (full-speed) or DM (low-speed). A dual-role device will
always initiate data line pulsing SRP through DP because it is a full-speed device.
Steps to enable the SRP detection by V
BUS
pulsing:
–
Set A_SEL_SRP (bit 9) of the OtgControl register to logic 0.
–
Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1.
Steps to enable the SRP detection by data line pulsing:
–
Set A_SEL_SRP (bit 9) of the OtgControl register to logic 1.
–
Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1.
Steps to disable the SRP detection:
–
Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 0.
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相關代理商/技術參數(shù)
參數(shù)描述
ISP1362EE,518 功能描述:USB 接口集成電路 USB OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1362EE,551 功能描述:USB 接口集成電路 DO NOT USE ORDER -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1362EE,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1362EE/01 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip Universal Serial Bus On-The-Go controller
ISP1362EE-S 功能描述:IC USB CTRL SNGL CHIP 64TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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