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參數(shù)資料
| 型號： | IS42S16100 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 512K Words x 16 Bits x 2 Banks (16-MBIT)Synchronous DRAM(512K x 16 x 2組同步動態(tài)RAM) |
| 中文描述： | 為512k字× 16位× 2銀行（16兆），同步DRAM（為512k × 16 × 2組同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 6/79頁 |
| 文件大?。?/td> | 656K |
| 代理商： | IS42S16100 |
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IS42S16100
ISSI
6
Integrated Silicon Solution, Inc.
—
1-800-379-4774
Rev. A
09/29/00
AC CHARACTERISTICS
(1,2,3)
-6
-7
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
t
CK
3
t
CK
2
t
AC
3
t
AC
2
t
CHI
t
CL
t
OH
3
t
OH
2
t
LZ
t
HZ
3
t
HZ
2
t
DS
t
DH
t
AS
t
AH
t
CKS
t
CKH
t
CKA
t
CS
t
CH
t
RC
t
RAS
t
RP
t
RCD
t
RRD
t
DPL
3
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2
CAS
Latency = 3
CAS
Latency = 2
6
8
—
—
2
2
2.5
2.5
0
—
—
2
1
2
1
2
1
—
—
5.5
6
—
—
—
—
—
5.5
6
—
—
—
—
—
—
—
—
—
—
7
—
—
6
6
—
—
—
—
—
6
6
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8.6
—
—
2.5
2.5
2.5
2.5
0
—
—
2
1
2
1
2
1
Access Time From CLK
(4)
CLK HIGH Level Width
CLK LOW Level Width
Output Data Hold Time
CAS
Latency = 3
CAS
Latency = 2
Output LOW Impedance Time
Output HIGH Impedance Time
(5)
CAS
Latency = 3
CAS
Latency = 2
Input Data Setup Time
Input Data Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
CKE to CLK Recovery Delay Time
Command Setup Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
Command Hold Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Active Command To Read / Write Command Delay Time
Command Period (ACT [0] to ACT[1])
Input Data To Precharge
Command Delay time
1CLK+3
2
1
60
42
18
16
12
1CLK
1CLK+3
2
1
63
42
20
16
14
1CLK
100,000
—
—
—
—
100,000
—
—
—
—
CAS
Latency = 3
t
DPL
2
t
DAL
3
CAS
Latency = 2
CAS
Latency = 3
1CLK
1CLK+t
RP
—
—
1CLK
1CLK+t
RP
—
—
ns
ns
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
t
DAL
2
t
T
t
REF
CAS
Latency = 2
1CLK+t
RP
1
—
—
10
128
1CLK+t
RP
1
—
—
10
128
ns
ns
ms
Transition Time
Refresh Cycle Time (4096)
Notes:
1. When power is first applied, memory operation should be started 100 μs after Vcc and VccQ reach their stipulated voltages. Also
note that the power-on sequence must be executed before starting memory operation.
2. Measured with t
T
= 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between V
IH
(min.) and V
IL
(max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time t
HZ
(max.) is defined as the time required for the output voltage to transition by ± 200 mV from V
OH
(min.) or V
OL
(max.)
when the output is in the high impedance state.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S16100_08 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16100-10T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| IS42S16100-10TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16100-5BL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16100-5TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
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