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參數(shù)資料
| 型號： | IS42S16100 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 512K Words x 16 Bits x 2 Banks (16-MBIT)Synchronous DRAM(512K x 16 x 2組同步動態(tài)RAM) |
| 中文描述： | 為512k字× 16位× 2銀行（16兆），同步DRAM（為512k × 16 × 2組同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 34/79頁 |
| 文件大?。?/td> | 656K |
| 代理商： | IS42S16100 |
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IS42S16100
ISSI
34
Integrated Silicon Solution, Inc.
—
1-800-379-4774
Rev. A
09/29/00
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42S16100 can input data continuously from the
burst start address (a) to location a+255 during a write
cycle in which the burst length is set to full page. The
IS42S16100 repeats the operation starting at the 256th
cycle with data input returning to location (a) and continuing
with a+1, a+2, a+3, etc. A burst stop command must be
executed to terminate this cycle. A precharge command
must be executed within the ACT to PRE command period
(t
RAS
max.) following the burst stop command. After the
period (t
WBD
) required for burst data input to stop following
the execution of the burst stop command has elapsed, the
write cycle terminates. This period (t
WBD
) is zero clock
cycles, regardless of the
CAS
latency.
CAS
latency = 2, burst length = 4
READ A0
COMMAND
UDQM
LDQM
I/O8-I/O15
I/O0-I/O 7
CLK
D
OUT
A0
t
QMD=2
HI-Z
HI-Z
HI-Z
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
D
OUT
A2
D
OUT
A3
D
OUT
A1
D
OUT
A0
Burst Data Interruption Using the
U/LDQM Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless
of the
CAS
latency, two clock cycles (t
QMD
) after one of the
U/LDQM pins goes HIGH, the corresponding outputs go
to the HIGH impedance state. Subsequently, the outputs
are maintained in the high impedance state as long as that
U/LDQM pin remains HIGH. When the U/LDQM pin goes
LOW, output is resumed at a time t
QMD
later. This output
control operates independently on a byte basis with the
UDQM pin controlling upper byte output (pins
I/O8-I/O15) and the LDQM pin controlling lower byte
output (pins I/O0 to I/O7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
CAS
latency = 2, 3, burst length = full page
WRITE A0
COMMAND
I/O
CLK
D
IN
A0
D
IN
A1
D
IN
A
D
IN
A1
D
IN
A2
t
WBD=0
t
RP
READ (CA=A, BANK 0)
BURST STOP
BST
PRE 0
INVALID DATA
PRECHARGE (BANK 0)
Don't Care
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PDF描述 |
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| IS42S16128 | 128K Words x 16 Bits x 2 Banks (4-Mbit)Synchronous DRAM(128K x 16 x 2組同步動態(tài)RAM) |
| IS42S16128-10T | 128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16128-12T | 128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16128-8T | Chassis Mount and Din Rail Filters RoHS Compliant: Yes |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S16100_08 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16100-10T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| IS42S16100-10TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16100-5BL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16100-5TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
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