參數(shù)資料
型號(hào): IS42S16100
廠商: Integrated Silicon Solution, Inc.
英文描述: 512K Words x 16 Bits x 2 Banks (16-MBIT)Synchronous DRAM(512K x 16 x 2組同步動(dòng)態(tài)RAM)
中文描述: 為512k字× 16位× 2銀行(16兆),同步DRAM(為512k × 16 × 2組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 31/79頁(yè)
文件大?。?/td> 656K
代理商: IS42S16100
IS42S16100
ISSI
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev. A
09/29/00
31
Precharge
The precharge command sets the bank selected by pin
A11 to the precharged state. This command can be
executed at a time t
RAS
following the execution of an active
command to the same bank. The selected bank goes to
the idle state at a time t
RP
following the execution of the
precharge command, and an active command can be
executed again for that bank.
If pin A10 is low when this command is executed, the bank
selected by pin A11 will be precharged, and if pin A10 is
HIGH, both banks will be precharged at the same time.
This input to pin A11 is ignored in the latter case.
CAS
Latency
t
RQL
3
3
2
2
Read Cycle Interruption
Using the Precharge Command
A read cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
RQL
) from the execution of the precharge
command to the completion of the burst output is the clock
cycle of
CAS
latency.
t
RQL
t
RQL
PRE 0
READ A0
COMMAND
I/O
CLK
D
OUT
A0
D
OUT
A1
D
OUT
A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
PRE 0
READ A0
COMMAND
I/O
CLK
D
OUT
A0
D
OUT
A1
D
OUT
A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS
latency = 2, burst length = 4
CAS
latency = 3, burst length = 4
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