參數(shù)資料
型號(hào): IS42S16100
廠商: Integrated Silicon Solution, Inc.
英文描述: 512K Words x 16 Bits x 2 Banks (16-MBIT)Synchronous DRAM(512K x 16 x 2組同步動(dòng)態(tài)RAM)
中文描述: 為512k字× 16位× 2銀行(16兆),同步DRAM(為512k × 16 × 2組同步動(dòng)態(tài)RAM)的
文件頁數(shù): 32/79頁
文件大?。?/td> 656K
代理商: IS42S16100
IS42S16100
ISSI
32
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev. A
09/29/00
CAS
latency = 2, 3, burst length = 4
CAS
latency = 2, 3, burst length = 4
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
WDL
) from the precharge command to the
point where burst input is invalid, i.e., the point where input
data is no longer written to device internal memory is zero
clock cycles regardless of the
CAS
.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual bank
operation.
PRE 0
WRITE A0
COMMAND
DQM
I/O
CLK
D
IN
A0
D
IN
A1
D
IN
A2
D
IN
A3
t
WDL
=0
PRECHARGE (BANK 0)
MASKED BY DQM
PRE 0
WRITE A0
COMMAND
I/O
CLK
D
IN
A0
D
IN
A1
D
IN
A2
D
IN
A3
t
DPL
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS
Latency
t
WDL
3
0
2
0
t
DPL
1
1
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write
data recovery period (t
DPL
) has elapsed. Therefore, the
precharge command must be executed on one clock cycle
that follows the input of the last burst data item.
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