參數(shù)資料
型號(hào): IS42S16100
廠商: Integrated Silicon Solution, Inc.
英文描述: 512K Words x 16 Bits x 2 Banks (16-MBIT)Synchronous DRAM(512K x 16 x 2組同步動(dòng)態(tài)RAM)
中文描述: 為512k字× 16位× 2銀行(16兆),同步DRAM(為512k × 16 × 2組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 1/79頁(yè)
文件大?。?/td> 656K
代理商: IS42S16100
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
09/29/00
1
IS42S16100
512K Words x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
ISSI
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2000, Integrated Silicon Solution, Inc.
FEATURES
Clock frequency: 166, 143, 125, 100 MHz
Fully synchronous; all signals referenced to a
positive clock edge
Two banks can be operated simultaneously and
independently
Dual internal bank controlled by A11 (bank select)
Single 3.3V power supply
LVTTL interface
Programmable burst length
– (1, 2, 4, 8, full page)
Programmable burst sequence:
Sequential/Interleave
Auto refresh, self refresh
4096 refresh cycles every 128 ms
Random column address every clock cycle
Programmable
CAS
latency (2, 3 clocks)
Burst read/write and burst read/single write
operations capability
Burst termination by burst stop and precharge
command
Byte controlled by LDQM and UDQM
Package 400-mil 50-pin TSOP II
DESCRIPTION
ISSI
's 16Mb Synchronous DRAM IS42S16100 is organized
as a 524,288-word x 16-bit x 2-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
SEPTEMBER 2000
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VCC
I/O0
I/O1
GNDQ
I/O2
I/O3
VCCQ
I/O4
I/O5
GNDQ
I/O6
I/O7
VCCQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
GNDQ
I/O13
I/O12
VCCQ
I/O11
I/O10
GNDQ
I/O9
I/O8
VCCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A11
Address Input
A0-A10
Row Address Input
A11
Bank Select Address
A0-A7
Column Address Input
I/O0 to I/O15
Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
WE
Write Enable
LDQM
Lower Bye, Input/Output Mask
UDQM
Upper Bye, Input/Output Mask
Vcc
Power
GND
Ground
VccQ
Power Supply for I/O Pin
GNDQ
Ground for I/O Pin
NC
No Connection
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