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| 型號： | intel Pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor Mobile Module(帶移動模塊奔II處理器) |
| 中文描述： | 奔騰II處理器的移動模塊（帶移動模塊奔二處理器） |
| 文件頁數(shù)： | 9/46頁 |
| 文件大小： | 681K |
| 代理商： | INTEL PENTIUM II PROCESSOR |
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9
INTEL
PENTIUM
II PROCESSOR MOBILE MODULE MMC-1
3.1.2.
Memory (108 Signals)
Table 2 lists the memory interface signals.
Table 2. Memory Signal Descriptions
Voltage
Name
Type
Description
MECC[7:0]
I/O
CMOS
V_3
Memory ECC Data:
These signals carry Memory ECC data during
access to DRAM.
These pins are not implemented on the MMC-1
and are reserved for future use.
RASA[5:0]# or
CSA[5:0]#
O
CMOS
V_3
Row Address Strobe (EDO):
These pins select the DRAM row.
Chip Select (SDRAM):
These pins activate the SDRAMs.
SDRAM
accepts any command when its CS# pin is active low.
CASA[7:0]# or
DQMA[7:0]
O
CMOS
V_3
Column Address Strobe (EDO):
These pins select the DRAM
column.
Input/Output Data Mask (SDRAM):
These pins act as
synchronized output enables during a read cycle and as a byte
mask during a write cycle.
MAB[9:0]#
MAB[10]
MAB[12:11]#
MAB[13]
O
CMOS
V_3
Memory Address (EDO/SDRAM):
This is the row and column
address for DRAM.
The 443BX Host Bridge system controller has
two identical sets of address lines (MAA and MAB#). The Pentium
II processor mobile module supports only the MAB set of address
lines. For additional addressing features, please refer to the Intel
440BX PCIset Datasheet
MWE[A, B]#
O
CMOS
O
CMOS
V_3
Memory Write Enable (EDO/SDRAM):
MWEA# should be used as
the write enable for the memory data bus.
SRAS[A, B]#
V_3
SDRAM Row Address Strobe (SDRAM):
When active low, this
signal latches Row Address on the positive edge of the clock. This
signal also allows Row access and pre-charge.
SCAS[A, B]#
O
CMOS
V_3
SDRAM Column Address Strobe (SDRAM):
When active low, this
signal latches Column Address on the positive edge of the clock.
This signal also allows Column access.
CKE[A, B]
O
CMOS
V_3
SDRAM Clock Enable (SDRAM):
When these signals are
deasserted, SDRAM enters power-down mode. CKEB is NC and
not used by the system electronics.
MD[63:0]
I/O
CMOS
V_3
Memory Data:
These signals are connected to the DRAM data bus.
They are not terminated on the Pentium
II processor mobile
module.
NOTES:
1.
2.
DQMA signals are non-inverted. Please refer to 82443BX Spec Update
MAB[13] is a non-inverted address signal. Please refer to 82443BX Spec Update.
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