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| 型號： | intel Pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor Mobile Module(帶移動模塊奔II處理器) |
| 中文描述： | 奔騰II處理器的移動模塊（帶移動模塊奔二處理器） |
| 文件頁數(shù)： | 21/46頁 |
| 文件大小： | 681K |
| 代理商： | INTEL PENTIUM II PROCESSOR |
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21
INTEL
PENTIUM
II PROCESSOR MOBILE MODULE MMC-1
4.4.
Power Management
4.4.1
Clock Control Architecture
The Pentium
II processor mobile module’s clock control
architecture (Figure 3) is optimal for notebook designs.
The clock control architecture consists of seven different
clock states: Normal, Stop Grant, Auto Halt, Quick Start,
HALT/Grant Snoop, Sleep, and Deep Sleep states.
The Auto Halt state provides a low power clock state that
can be controlled through the software execution of the HLT
instruction. The Quick Start state provides a very low power,
low exit latency clock state that can be used for hardware
controlled “idle” computer states. The Deep Sleep State
provides an extremely low power state that can be used for
“Power-on Suspend” computer states, which is an alternative
to shutting off the processor’s power.
Compared to the Pentium processor mobile module exit
latency of 1 msec, the exit latency of the Deep Sleep state
has been reduced to 30
μ
sec in the Pentium II processor
mobile module.
The Stop Grant and Quick Start clock states are mutually
exclusive, for example a strapping option on signal A15#
chooses which state is entered when the STPCLK# signal is
asserted. Strapping the A15# signal to ground at Reset
enables the Quick Start state. Otherwise, asserting the
STPCLK# signal puts the Pentium II processor into the Stop
Grant state. The Stop Grant state has a higher power level
than the Quick Start state and is designed for SMP
platforms. The Quick Start state has a much lower power
level, but it can only be used in uniprocessor (UP) platforms.
Performing state transitions not shown in Figure 3 is neither
recommended nor supported.
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