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| 型號： | intel Pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor Mobile Module(帶移動模塊奔II處理器) |
| 中文描述： | 奔騰II處理器的移動模塊（帶移動模塊奔二處理器） |
| 文件頁數(shù)： | 14/46頁 |
| 文件大小： | 681K |
| 代理商： | INTEL PENTIUM II PROCESSOR |
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14
INTEL
PENTIUM
II PROCESSOR MOBILE MODULE MMC-1
3.1.7
Voltages (39 Signals)
Table 7 lists the voltage signal definitions.
Table 7. Voltage Descriptions
Name
Type
Number
Description
V_DC
I
10
DC Input:
5V - 21V
V_3S
I
20
SUSB# controlled 3.3V:
Power-managed 3.3V supply.
An output of the
voltage regulator on the system electronics. This rail is off during STR,
STD, and Soff.
V_5
I
1
SUSC# controlled 5V:
Power-managed 5V supply.
An output of the
voltage regulator on the system electronics. This rail is off during STD
and Soff.
V_3
I
5
SUSC# controlled 3.3V:
Power-managed 3.3V supply.
An output of the
voltage regulator on the system electronics. This rail is off during STD
and Soff.
V_CPUIO
O
3
Processor I/O Ring:
Powers processor interface signals such as the
PIIX4E open-drain pullups for the processor/PIIX4E sideband signals
and the CKDM66-M clock source.
3.1.8
JTAG (7 Signals)
Table 8 lists the ITP/JTAG signals, which the system
electronics can use to implement a JTAG chain and ITP port,
if desired. The JTAG signals provided can not be used as an
ITP port, since the definition of the ITP interface has
changed between the Pentium
processor and mobile
Pentium II processor generations.
Table 8. JTAG Pins
Name
Type
Voltage
Description
TDO
O
V_CPUIO
JTAG Test Data Out:
Serial output port. TAP instructions and
data are shifted out of the processor from this port.
TDI
I
V_CPUIO
JTAG Test Data In:
Serial input port. TAP instructions and data
are shifted into the processor from this port.
TMS
I
V_CPUIO
JTAG Test Mode Select:
Controls the TAP controller change
sequence.
TCLK
I
V_CPUIO
JTAG Test Clock:
Testability clock for clocking the JTAG
boundary scan sequence.
TRST#
I
V_CPUIO
JTAG Test Reset:
Asynchronously resets the TAP controller in
the processor.
ITP(1:0)
ITP1
ITP0
O
I
V_CPUIO
Debug Port Signals:
Currently defined for the generation of
Pentium
processors. These signals are not used in the Pentium
II processor mobile module, and should not be connected.
NOTE:
DBREST# (reset target system) on the ITP debug port can be “l(fā)ogically ANDed” with VR_PWRGD TO PIIX4E’s PWROK.
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