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參數(shù)資料
| 型號： | intel Pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor Mobile Module(帶移動模塊奔II處理器) |
| 中文描述： | 奔騰II處理器的移動模塊（帶移動模塊奔二處理器） |
| 文件頁數(shù)： | 29/46頁 |
| 文件大?。?/td> | 681K |
| 代理商： | INTEL PENTIUM II PROCESSOR |
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29
INTEL
PENTIUM
II PROCESSOR MOBILE MODULE MMC-1
4.7.2.1.
Voltage Signal Definition and Sequencing
Table 19. Voltage Signal Definitions and Sequences
Source
Signal
Definitions and Sequences
V_DC
System Electronics
DC voltage is driven from the power supply and is
required to be between 5V and 21V DC. V_DC
powers the Pentium
II processor mobile module’s
DC-to-DC converter for processor core and I/O
voltages. It cannot be hot inserted or removed while
V_DC is powered on.
V_3
System Electronics
V_3 is supplied by the system electronics for the
443BX.
V_5
System Electronics
V_5 is supplied by the system electronics for the
443BX’s reference voltage and the voltage regulator.
V_3S
System Electronics
V_3S is supplied by the system electronics for the L2
cache devices. Each must be powered off during
system STR and STD states.
VR_ON
System Electronics
Enables the voltage regulator circuit. When driven
active high (3.3V) the voltage regulator circuit is
activated. The signal driving VR_ON should be a
digital signal with a rise/fall time of less than or equal
to 1
μ
s. (VIL (max)=0.4V, VIH (min)=3.0V). See notes
below.
V_CORE (also
used as host bus
GTL+ termination
voltage VTT)
Pentium
II processor mobile
module Only; not on module
interface.
A result of VR_ON being asserted, V_CORE is an
output of the DC-DC regulator on the Mobile Module
and is driven to the core voltage of the processor. It is
also used as the host bus GTL+ termination voltage,
known as VTT.
V_BSB_IO
Pentium
II processor mobile
module
V_BSB_IO is 1.8V. The system electronics uses this
voltage to power the L2 cache-to-processor interface
circuitry.
VR_PWRGD
Pentium
II processor mobile
module
Upon sampling the voltage level of V_CORE (minus
tolerances for ripple), VR_PWRGD is driven active
high. If VR_PWRGD is not sampled active within 1
sec. of the assertion of VR_ON, then the system
electronics should deassert VR_ON. After Vcore is
stabilized, VR_PWRGD will assert to logic high
(3.3V). This signal
must not be pulled up
by the
system electronics. VR_PWRGD should be “ANDed”
with V_3s to generate the PIIX4E input signal,
PWROK. The system electronics should monitor
VR_PWRGD to verify it is asserted high prior to the
active high assertion of PIIX4E PWROK.
V_CPUIO
Pentium
II processor mobile
module
V_CPUIO is 2.5V. The system electronics uses this
voltage to power the PIIX4E-to-processor interface
circuitry, as well as the HCLK(0:1) drivers for the
processor clock.
NOTES
:
1.
The VR_ON signal may only be asserted to a logical high by a digital signal only after V_DC>=4.7V, V_5>=4.5V, and V_3>=
3.0V.
The rise time and fall time of VR_ON must be less than or equal to 1
μ
s when it goes through its Vil to Vih.
VR_ON has its Vil (max) = +0.4V and Vih (min) = + 3.0V.
VR_ON needs to rise monotonically through its Vil to Vih points.
VR_ON needs to provide an instantaneous in-rush current to the module with the following values: an instantaneous max. of
41 mA with a typical of 0.2 mA; a DC operating max. of 0.1
μ
A with a typical of 0.0.
In going from a valid on to valid off and then back on, VR_ON must be low for 1 ms. In addition, the original voltage level
requirements for turn-on always need to be met before assertion of VR_ON (i.e. V_DC>=4.7V, V5>=4.5V, V_3>=3.0V).
2.
3.
4.
5.
6.
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