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參數(shù)資料
| 型號： | intel Pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor Mobile Module(帶移動模塊奔II處理器) |
| 中文描述： | 奔騰II處理器的移動模塊（帶移動模塊奔二處理器） |
| 文件頁數(shù)： | 24/46頁 |
| 文件大?。?/td> | 681K |
| 代理商： | INTEL PENTIUM II PROCESSOR |
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24
INTEL
PENTIUM
II PROCESSOR MOBILE MODULE MMC-1
the Sleep state. Input signal changes at these times will
cause unpredictable behavior. Thus, the processor is
incapable of snooping or latching any events in the Sleep
state.
While in the Sleep state the processor can enter its lowest
power state, the Deep Sleep state. Removing the
processor’s input clock puts the processor in the Deep Sleep
state. PICCLK may be removed in the Sleep state.
The Sleep state is not supported in Intel mobile modules.
4.4.8.
Deep Sleep State
The Deep Sleep state is the lowest power mode the
processor can enter while maintaining its context. The Deep
Stopping the BCLK input to the processor enters sleep state,
while it is in the Sleep state or Quick Start state. For proper
operation, the BCLK input should be stopped in the low
state.
The processor will return to the Sleep state or Quick Start
state from the Deep Sleep state when the BCLK input is
restarted. Due to the PLL lock latency, there is a 30-msec
delay after the clocks have started before this state transition
happens. PICCLK may be removed in the Deep Sleep state.
PICCLK should be designed to turn on when BCLK turns on
when transitioning out of the Deep Sleep state.
The input signal restrictions for the Deep Sleep state are the
same as for the Sleep state, except that RESET# assertion
will result in unpredictable behavior.
Table 13. Mobile Pentium
II Processor Clock State Characteristics
Exit Latency
Processor
Clock
State
Power
Snooping
System Uses
Normal
N/A
Varies
Yes
Normal program execution.
Auto Halt
Approximately 10 bus clocks
1.2 W
Yes
S/W controlled entry idle
mode.
Stop Grant
10 bus clocks
1.2 W
Yes
H/W controlled entry/exit
mobile throttling.
Quick Start
Through snoop, to HALT/Grant
Snoop state: immediate
Through STPCLK#, to Normal
state: 10 bus clocks
0.5 W
Yes
H/W controlled entry/exit
mobile throttling.
HALT/Grant
Snoop
A few bus clocks after the end of
snoop activity.
Not
specified
Yes
Supports snooping in the
low power states.
Sleep
To Stop Grant state 10 bus clocks
0.5 W
No
H/W controlled entry/exit
desktop idle mode support.
Deep Sleep
30 msec
150 mW
No
H/W controlled entry/exit
mobile powered-on suspend
support.
NOTE:
Not 100% tested. Specified at 50
°
C by design/characterization.
4.5.
Typical POS/STR Power
Table 14 shows the POS/STR power values.
Table 14. Mobile Pentium
II Processor POS/STR Power
State
Typical MMC1 Power
POS
910 mW
STR
3 mW
NOTE:
These are average values of measurement on several typical modules and are guidelines only.
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