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參數(shù)資料
| 型號(hào)： | intel Pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor Mobile Module(帶移動(dòng)模塊奔II處理器) |
| 中文描述： | 奔騰II處理器的移動(dòng)模塊（帶移動(dòng)模塊奔二處理器） |
| 文件頁數(shù)： | 30/46頁 |
| 文件大?。?/td> | 681K |
| 代理商： | INTEL PENTIUM II PROCESSOR |
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INTEL
PENTIUM
II PROCESSOR MOBILE MODULE MMC-1
POWER SEQUENCE TIMING
V_DC
1. PWROK on I/O board should be active on when VR_PWRGD is active and V_3S is good.
2. CPU_RST from I/O board should be active for a minimum of 6 ms after PWROK is active and PLL_STP# and CPU_STP# are
inactive. Note that PLL_STP# is an AND condition of RSMRST# and SUSB# on the PIIX4E/M.
3. V_DC >= 4.7V, V_5>=4.5V, V_3S>=3.0V.
4. V_CPUPU and V_CLK are generated on the Intel Mobile Module.
5. This is the 5V power supplied to the processor module connector. This should be the first 5V plane to power up.
6. VR_PWRGD is specifiedto its associated high/active by the module regulator within less than or equal to 6 ms max. after the
assertion of VR_ON.
Figure 5. Power-On Sequence Timing
V_3
V_5
VR_PWRGD
V_3S
VR_ON
0 MS MIN
0 MS MIN
0 MS MIN
See Note 6
See Note 3
V_CPUIO/
V_CLK
See Note 5
In the power-on process, Intel recommends that the higher
voltage power (V_DC) plane is raised first, followed by the
lower power planes (V_5 and V_3), and finally the assertion
of VR_ON. In the power-off process, the reverse applies so
that first VR_ON is deasserted, followed by the lower power
planes, and finally the higher power plane.
4.7.3.
Power Planes: Bulk Capacitance
Requirements
In order to provide adequate filtering and in-rush current
protection for any system design, bulk capacitance is
required. A small amount of bulk capacitance is supplied on
the Pentium
II processor mobile module. However, in order
to achieve proper filtering additional capacitance should be
placed on the system electronics.
Table 20 details the bulk capacitance requirements for the
system electronics when using the Pentium II processor
mobile module.
Table 20. Capacitance Requirements per Power Plane
Capacitance Requirements
Power Plane
ESR
Ripple Current
Rating
V_DC
100 uf, 0.1 uf, 0.01 uf
1
20 m
1-3.5A
3
20% tolerance at 35V
V_5
100 uf, 0.1 uf, 0.01 uf
1
100 m
1A
20% tolerance at 10V
V_3
470 uf, 0.1 uf, 0.01 uf
1
100 m
1A
20% tolerance at 6V
V_3S
100 uf, 0.1 uf, 0.01 uf
1
100 m
N/A
20% tolerance at 6V
V_CPUIO
2.2 uf, 8200 pf
1
n/a
n/a
20% tolerance at 6V
NOTES:
1.
2.
3.
Placement of above capacitance requirements should be located near the MMC-1.
V_CPUIO filtering should be located next to the system clock synthesizer.
Ripple current specification depends on V_DC input. For 5.0V V_DC, a 3.5A device is required. For V_DC at 18V or higher,
1A is sufficient.
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