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| 型號(hào)： | intel Pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor Mobile Module(帶移動(dòng)模塊奔II處理器) |
| 中文描述： | 奔騰II處理器的移動(dòng)模塊（帶移動(dòng)模塊奔二處理器） |
| 文件頁數(shù)： | 10/46頁 |
| 文件大?。?/td> | 681K |
| 代理商： | INTEL PENTIUM II PROCESSOR |
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10
INTEL
PENTIUM
II PROCESSOR MOBILE MODULE MMC-1
3.1.3.
PCI (56 Signals)
Table 3 lists the PCI interface signals.
Table 3. PCI Signal Descriptions
Voltage
Name
Type
Description
AD[31:0]
I/O
PCI
V_3
Address/Data:
The standard PCI address and data lines. The
address is driven with FRAME# assertion, and data is driven or
received in following clocks.
C/BE[3:0]#
I/O
PCI
V_3
Command/Byte Enable:
The command is driven with FRAME#
assertion and byte enables corresponding to supplied or
requested data are driven on the following clocks.
FRAME#
I/O
PCI
V_3
Frame:
Assertion indicates the address phase of a PCI transfer.
Negation indicates that one more data transfers are desired by the
cycle initiator.
DEVSEL#
I/O
PCI
V_3
Device Select:
The 443BX Host Bridge drives this signal when a
PCI initiator is attempting to access DRAM.
DEVSEL# is asserted
at medium decode time.
IRDY#
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
V_3
Initiator Ready:
Asserted when the initiator is ready for data
transfer.
TRDY#
V_3
Target Ready:
Asserted when the target is ready for a data
transfer.
STOP#
V_3
Stop:
Asserted by the target to request the master to stop the
current transaction.
PLOCK#
V_3
Lock:
Indicates an exclusive bus operation and may require
multiple transactions to complete. When LOCK# is asserted, non-
exclusive transactions may proceed. The 443BX supports lock for
CPU initiated cycles only. PCI initiated locked cycles are not
supported.
REQ[4:0]#
I
PCI
O
PCI
I
PCI
V_3
PCI Request:
PCI master requests for PCI.
GNT[4:0]#
V_3
PCI Grant:
Permission is given to the master to use PCI.
PHOLD#
V_3
PCI Hold:
This signal comes from the expansion bridge; it is the
bridge request for PCI.
The 443BX Host Bridge will drain the
DRAM write buffers, drain the processor-to-PCI posting buffers,
and acquire the host bus before granting the request via PHLDA#.
This ensures that GAT timing is met for ISA masters.
The
PHOLD# protocol has been modified to include support for
passive release.
PHLDA#
O
PCI
V_3
PCI Hold Acknowledge:
The 443BX Host Bridge drives this
signal to grant PCI to the expansion bridge. The PHLDA# protocol
has been modified to include support for passive release.
PAR
I/O
PCI
I/O
PCI
V_3
Parity:
A single parity bit is provided over AD[31:0] and
C/BE[3:0]#.
SERR#
V_3
System Error:
The 443BX asserts this signal to indicate an error
condition. Please refer to the Intel
440BX PCIset Datasheet
(Order Number 290633-001) for further information.
CLKRUN#
I/O D
PCI
V_3
Clock Run:
An open-drain output and input.
The 443BX Host
Bridge requests the central resource (PIIX4E) to start or maintain
the PCI clock by asserting CLKRUN#.
The 443BX Host Bridge tri-
states CLKRUN# upon deassertion of Reset (since CLK is running
upon deassertion of Reset).
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