參數資料
型號： IDT88P8344BHI
廠商： IDT, Integrated Device Technology Inc
文件頁數： 83/98頁
文件大?。?/td> 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標準包裝： 24
系列： *
其它名稱： 88P8344BHI
84
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Inputs
Unit
Min.
Typ.
Max.
Description
Duty cycle
%
45
50
55
I_DCLK ingress clock duty cycle
Frequency (DDR)
MHz
80
—
200
Ingress clock frequency, I_LOW=1
Frequency (DDR)
MHz
200
311
400
Ingress clock frequency, I_LOW=0
TR, TF
ps
300
—
500
Input rise or fall time ( 20%, 80% )
Deskew
UI
—
+/- 1
Bit line deskew
Outputs
Duty cycle
%
45
50
55
E_DCLK Egress clock duty cycle
Frequency (DDR)
MHz
80
—
200
Egress clock frequency, E_LOW=1
Frequency (DDR)
MHz
200
311
400
Egress clock frequency, E_LOW=0
TR, TF
ps
300
—
500
Output rise or fall time ( 20%, 80% )
Tskew
ps
—
50
Output differential skew, P to N
SYNTH Jitter
UI
—
0.1
PLL jitter as a fraction of the clock cycle
TD
ns
—
Adjustable
TABLE 133 – SPI-4.2 LVDS AC INPUT / OUTPUT TIMING SPECIFICATIONS
REF_CLK
Unit
Min.
Typ.
Max.
Duty cycle
%
30
50
70
REF_CLK clock input duty cycle
FREF_CLK
MHz
12.5
19.44
25
Main reference clock input
TR, TF
ns
—
5
Rise fall time ( 20%, 80% )
11.6.4 REF_CLK clock input
11.6.5 MCLK internal clock and OCLK[3:0] clock outputs
OCLK[3:0]
Unit
Min.
Typ.
Max.
Description
Duty cycle
%
45
50
55
OCLK[3:0] outputs, clock duty cycle
Frequency
MHz
40
104
133
OCLK[3:0], programmable
Outputskew
One pll_oclk cycle of deliberate
between OCLKs
skew between each OCLK[3:0]
TR, TF
ns
1
2
OCLK[3:0] rise, fall time (20%,80%)
MCLK
Frequency
MHz
80
—
100
Programmable
11.6.6 Microprocessor interface
All outputs
Unit
Min.
Typ.
Max.
Description
TR, Tf
ns
10
Rise, fall time (20%, 80%)
All inputs
TR, TF
ns
10
Rise, fall time (20%,80%)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SPI-4 LVTTL Status(1)
STAT_T[1:0] to SCLK_T setup time
TSU
2ns
SCLK_T to STAT_T [1:0] hold time
TH
0.5
ns
SCLK_T to STAT_T [1:0] delay
TD
1
1.2
ns
11.6.3 SPI-4 LVTTL Status AC characteristics
TABLE 134 – SPI-4 LVTTL STATUS AC CHARACTERISTICS
TABLE 135 – REF_CLK CLOCK INPUT
TABLE 136 – OCLK[3:0] CLOCK OUTPUTS AND MCLK INTERNAL CLOCK
TABLE 137 – MICROPROCESSOR INTERFACE
NOTE:
1. For the SPI-4 LVTTL valid, hold & setup the edge is configurable. The SPI-4 ingress LVTTL status clock active edge is
configured by I_CLK_EDGE field in Table 89-SPI-4 Ingress Configuration Register on page 69. The SPI-4 egress LVTTL
status clock active edge is configured by E_CLK_EDGE field in Table 104-SPI-4 Egress Configuration Register on page 73.
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