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參數(shù)資料
| 型號(hào)： | IDT88P8344BHI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 39/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88P8344BHI |
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44
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
example,aSPI-4clockof400MHzgivesadataunitintervalof1.25ns,somatch
the lengths within the entire signal group to within 625 ps, or 3 inches.
3) Keep P and N signals within a differential pair on the same layer with the
minimumtracespacingpossiblewhilestillbeingabletoget100ohmsdifferential
impedance (tightly edge-coupled pair routing).
4) Route all differential pairs as 100 Ohm embedded differential stripline (on
an inner layer, referencing ground planes). For example, 7 mil wide 1/2 oz
copper traces separated by 10 mils, with 10 mil dielectric spacing to ground
planes above and below the traces gives 100 Ohms of differential impedance
for FR-4 with a relative dielectric constant (
ε
R or DK) of 4.2. If the edge to edge
spacingbetweenadjacentdifferentialpairtracesis20mils,crosstalkis0.6%for
signalsterminatedtowithina10%impedancematch.Iftheedgetoedgespacing
betweenadifferentialpairandanLVTTLsignalis30milswithintheparameters
of this example, crosstalk is 0.8% (with the LVTTL signals series terminated).
Use a field solver for more accurate results.
5) Follow the SPI-3 layout guidelines for any routed SPI-4 LVTTL status
signals.
GENERAL LAYOUT GUIDELINES
1)KeepLVDSsignalsfarfromLVTTLsignals:atleastthreetimesthedielectric
thicknesstothereferenceplane(orthreetimesthetraceseparation,whichever
isgreater)inseparationwidth,tominimizethecrosstalkcontributionofnoiseon
the LVDS signals from the noisy LVTTL environment.
2)Separatesignalsofthesametypebyatleasttwicethedielectricthickness
(or twice the trace separation, whichever is greater) to the reference plane to
reduce crosstalk.
3)Thereferenceplanesmustextendatleastfivetimesthedielectricthickness
from either side of the trace and be unbroken.
4) Avoid changing layers on high-speed signals. On a layer change, signals
should share the same reference (such as ground), connected by reference
viasclosetothesignalviasforgoodcurrentreturn.Ifadifferentreferenceplane
(such as Vcc) must be used due to a signal layer change, good high-frequency
0.01
Fceramiccapacitorsmustbeusedtoconnectthereferencestogether
asclosetothesignalviasaspossibletoensuregoodtransmissionlineproperties
and current return.
5)Useofalow-jitter(100picosecondspeak-peakmaximumjitter)frequency
source for REF_CLK is important. If I_DCLK is used instead of REF_CLK,
ensure that I_DCLK is low in jitter and always available.
6) Keep the power decoupling capacitors as close as possible to the power
pins, using at least 15 mil traces and double vias for reduced inductance where
possible.
7) Distribute some large-valued capacitors around the board for low-
frequency decoupling and to lower the power-supply impedance.
8) TRSTB (JTAG reset) must have a pull down resistor or be connected to
RESETB for normal operation.
9) Filter the 1.8 Volt and 3.3 Volt analog power pins to isolate them from the
noisy digital environment. Use ferrite beads and capacitors (Pi filters) for
VDDA18_x and VDDA33.
10) Suppress non-functional inner layer pads.
8.2.7 Software Eye-Opening Check on SPI-4
Interface
Since the SPI-4 interface is a DDR interface, both rising and falling edges
are used to update or sink data.
dn
dn+1
01
234567
89abc
c0
c5
c9
clock
data
over sample
position
counter
c1
c6
c4
c2
c7
c3
c8
6370 drw23b
Figure 33. DDR interface and eye opening check through over sampling
Refer to the IDT88P8344 uses an internal sampling clock cycle which has
afrequencyof10timesSPI-4clocktoover-samplethedataonalane.Foreach
sampling clock cycle t position n data are sampled and labeled as R
t.dn. The
following operation is then performed:
CNT
0= Rt.d2^ Rt.d3
CNT
1= Rt.d3^ Rt.d4
CNT
2= Rt.d4^ Rt.d5
CNT
3= Rt.d5^ Rt.d6
CNT
4= Rt.d6^ Rt.d7
CNT
5= Rt.d7^ Rt.d8
CNT
6= Rt.d8^ Rt.d9
CNT
7= Rt.d9^ Rt+1.d0
CNT
9= Rt+1.d0^ Rt+1.d1
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