參數(shù)資料
型號(hào)： IDT88P8344BHI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 36/98頁(yè)
文件大?。?/td> 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8344BHI
41
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
8. OPERATION GUIDE
8.1 Hardware operation
8.1.1 System reset
There are two methods for resetting the device: hardware reset & software
reset. During reset the output clocks are not toggled.
Hardware reset
The RESETB input requires an active low pulse to reset the internal logic.
Software reset
The software reset is triggered by setting to 1 the SW_RESET field in direct
register Software Reset Register (p.51). The response to a software reset is
identical to a hardware rest except that software reset does not change the
N_OCLK[3:0] fields in the Clock Generator Control Register (p.77), so it does
not impact the clock generators. The SW_RESET field is self-clear to 0 after the
device initialized itself.After software reset the external microprocessor should
have delay of at least 1ms before accessing the device, and then.After the 1ms
delay, the user should poll the INIT_DONE field in the Software Reset Register
(p.51), and wait till it is 1. When the INIT_DONE field is 1, the user should
download a boot code from the external microprocessor flash to the device
embedded processor RAM.
8.1.2 Power on sequence
A correct power-on-reset sequence is crucial for the normal behavior of
the device. The power-on-reset sequence includes the following signals:
CLK (REF_CLK or I_DCLK - depends on which of theses pins are selected),
VDDT33, VDDC12 and RESETB. Figure 32, Power-on-Reset Sequence
illustrates the recommended implementation for the power-on-reset sequence
for the device. IDT recommends powering up the VDD33 power supply first,
and the VDDC18 power supply last. The power supplies can be also powered
up in the same time. There is no requirement for the minimum or maximum
delay between the power-up of the power supplies. The power supplies
should be powered off in the revers order. The power ramp should not be fast
than 100us, but also not too slow.
When the power supplies are powered up, the RESETB signal should be
at low level. During power-on-reset, after the VDDT33, VDDC18, CLK
(REF_CLK or I_DCLK - depends on which of theses pins are selected) and
the configuration signals are stable, the RESETB signal should remain at a low
level at least 10ms (symbol “T1”) to reset the internal logic. After the RESETB
pulse ends, the device starts generating the SPI-4 / SPI-3 external output
clocks & the MCLK internal clock.
After the RESETB pulse ends, a delay of 1ms should be added (symbols
“T2”) before accessing the device for initialization and configuration. This
allows the internal logic to be stable. During T2 (at least 1ms delay) the device
performs internal memories initialization.
After T2, the user should poll the INIT_DONE field in the in the Software
Reset Register (p.51), and wait till it is 1. When the INIT_DONE field is 1, the
user should download a boot code from the external microprocessor flash to
the device embedded processor RAM.
T1
CLK
VDDT33
RESETB
T2
VDDC18
6370 drw23a
8.1.3 Clock domains
The chip has several clock domains. The related registers can not be
configured without each clock. It is necessary to supply the clocks that are
pertinenttotheregistersbeinginitializedfortheinitializationtosucceed.Inorder
toaccessthemicroprocessorinterface,MCLKmustbeactive,eitherbyselecting
andprovidingastableREF_CLKinput,orbyselectingandensuringthatastable
clock is always present on the I_DCLK input. The selection of either the
REF_CLK or the I_DCLK clock inputs is described in Table 14 CK_SEL[3:0]
input pin decoding.
8.2 Software operation
8.2.1 Chip configuration sequence
Forproperdeviceoperation,itisimportanttoinitializetheIDT88P8344inthe
correct sequence following reset. This sequence is outlined in the following
paragraphs.
1) Reset the IDT88P8344 chip. After reset, the chip will perform auto
initialization.Waitforthechipinitializationtocomplete.TheINIT_DONEflagwill
go high when initialization has been completed.
Figure 32. Power-on-Reset Sequence
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