參數(shù)資料
型號： IDT88P8344BHI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 65/98頁
文件大?。?/td> 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8344BHI
68
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
9.4 Common module indirect registers
(Module_base 0x8000)
Table Number, Page
Block_base, Register_offset
Title of Register
86, page 69
0x0000, 0x00-0xFF
SPI-4 ingress LP to LID map
87, page 69
0x0100, 0x00-0xFF
SPI-4 ingress calendar_0
88, page 69
0x0200, 0x00-0xFF
SPI-4 ingress calendar_1
89, page 69
0x0300, 0x00
SPI-4 ingress configuration register
90, page 70
0x0300, 0x01
SPI-4 ingress status configuration register
91, page 70
0x0300, 0x02
SPI-4 ingress status register
92, page 70
0x0300, 0x03
SPI-4 ingress inactive transfer port
93, page 71
0x0300, 0x04-0x05
SPI-4 ingress calendar configuration register
94, page 71
0x0300, 0x06
SPI-4 ingress watermark register
95, page 71
0x0300, 0x07-0x0A
SPI-4 ingress fill level register
96, page 71
0x0300, 0x0B-0x0E
SPI-4 ingress max fill level register
97, page 71
0x0300, 0x0F
SPI-4 ingress diagnostics register
98, page 72
0x0300, 0x10
SPI-4 ingress DIP-4 error counter
99, page 72
0x0300, 0x11
SPI-4 ingress bit alignment control register
100, page 72
0x0300, 0x12
SPI-4 ingress start up training threshold register
101, page 72
0x0400, 0x00-0xFF
SPI-4 egress LID to LP map
102, page 72
0x0500, 0x00-0xFF
SPI-4 egress calendar_0
103, page 73
0x0600, 0x00-0xFF
SPI-4 egress calendar_1
104, page 73
0x0700, 0x00
SPI-4 egress configuration register_0
105, page 73
0x0700, 0x01
SPI-4 egress configuration register_1
106, page 74
0x0700, 0x02
SPI-4 egress status register
107, page 74
0x0700, 0x03-0x04
SPI-4 egress calendar configuration register
108, page 74
0x0700, 0x05
SPI-4 egress diagnostics register
109, page 74
0x0700, 0x06
SPI-4 egress DIP-2 error counter
110, page 75
0x0800, 0x00
SPI-4 ingress bit alignment window register
111, page 75
0x0800, 0x01
SPI-4 ingress lane measure register
112, page 75
0x0800, 0x02-0x0B
SPI-4 ingress bit alignment counter register
113, page 75
0x0800, 0x0C-0x1F
SPI-4 ingress manual alignment phase/result register
114, page 75
0x0800, 0x2A
SPI-4 egress data lane timing register
115, page 76
0x0800, 0x2B
SPI-4 egress control lane timing register
116, page 76
0x0800, 0x2C
SPI-4 egress data clock timing register
117, page 76
0x0800, 0x2D
SPI-4 egress status timing register
118, page 76
0x0800, 0x2E
SPI-4 egress status clock timing register
119, page 77
0x0900, 0x00
PMON timebase control register
120, page 77
0x0900, 0x01
Timebase register
121, page 77
0x0900, 0x10
Clock generator control register
122, page 77
———————-
OCLK and MCLK frequency select encoding
123, page 78
0x0900, 0x20
GPIO register
124, page 78
0x0900, 0x21– 0x25
GPIO monitor table
125, page 78
0x0900, 0x30
Version number register
TABLE 85 -COMMON MODULE (MODULE_BASE
0x8000) INDIRECT REGISTER TABLE
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