參數(shù)資料
型號(hào)： IDT88P8344BHI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 48/98頁(yè)
文件大?。?/td> 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8344BHI
52
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Software reset
The SPI-4 Status Register (0x22 in the direct accessed space) has read
access, and interrupt status fields are cleared by a microprocessor write cycle,
where a logical one must be written to clear the field(s) targeted.
The SPI-4 Status Register is a secondary interrupt status register and can
only be active if the SPI-4 field is active in the Primary Interrupt Status Register
(Direct 0x2C).
I_DIP_ERR_I
SPI-4 ingress DIP-4 error interrupt indication.
0=No errors
1=One or more DIP-4 errors have been registered on the SPI-4 ingress
I_SYNCH_I
SPI-4 ingress data path has transitioned from out of
synchronization to in synchronization condition interrupt indication.
0=No detection, still not in synchronization
1=Transition from out of synchronization to in synchronization, or transition
from in synchronization to out of synchronization
I_BUS_ERR_I SPI-4 ingress bus error interrupt indication.
0=No errors
1=One or more bus errors have been registered on the SPI-4 ingress
SPI4_INACTIVE_TRANSFER_I
SPI-4ingressinactivetransferinter-
ruptindication.
0=Noindication
1=OneormoreinactivetransfershavebeenregisteredontheSPI-4ingress
DCLK_UN_I
SPI-4 ingress data clock has transitioned from available
to an unavailable condition interrupt indication.
0=No detection, I_DCLK is available
1=I_DCLK transitioned from available to an unavailable state
E_DIP_ERR_I
SPI-4 egress DIP-2 error interrupt indication on the SPI-
4 egress status channel.
0=No errors
1=One or more DIP-2 errors have been registered
E_SYNCH_I
SPI-4 egress status channel has transitioned from out of
synchronization to an in synchronization condition interrupt indication.
0=No detection, still not in synchronization
1=Transition from out of synchronization to in synchronization, or transition
from in synchronization to out of synchronization
SCLK_UN_I
SPI-4egressstatusclockhastransitionedfromavailable
to an unavailable condition interrupt indication.
In LVTTL mode the Bridgeport does not detect the SPI-4 egress status clock
(E_SCLK_T). Therefore, for LVTTL mode the software should ignore the
SCLK_UN field in the SPI-4 Status Register.
0=No detection, E_SCLK is available
1=E_SCLK transitioned from available to an unavailable state
SPI-4 enable register (0x23 in the direct accessed
space)
The SPI-4 Enable Register (0x23 in the direct accessed space) has read
andwriteaccess.SPI-4EnableRegisterisusedtobitwiseenabletheinterrupts
in the SPI-4 Status Register.
I_DIP4_ERR_EN SPI-4 ingress DIP-4 error interrupt indication enable.
0=Disable DIP-4 error interrupt
1=Enable DIP-4 error interrupt
Field
Bits
Length
Initial Val
I_DIP4_ERR_EN
0
1
0
I_SYNCH_EN
1
0
I_BUS_ERR_EN
2
1
0
SPI4_INACTIVE_TRANSFER_EN
3
1
0
DCLK_UN_EN
4
1
0
E_DIP_ERR_EN
5
1
0
E_SYNCH_EN
6
1
0
SCLK_UN_EN
7
1
0
TABLE 41 - SPI-4 ENABLE REGISTER (0x23 IN
THEDIRECTACCESSEDSPACE)
Field
Bits
Length
Initial Val
I_DIP_ERR_I
0
1
0
I_SYNCH_I
1
0
I_BUS_ERR_I
2
1
0
SPI4_INACTIVE_TRANSFER_I
3
1
0
DCLK_UN_I
4
1
0
E_DIP_ERR_I
5
1
0
E_SYNCH_I
6
1
0
SCLK_UN_I
7
1
0
TABLE 40 - SPI-4 STATUS REGISTER (0x22 IN THE
DIRECTACCESSEDSPACE)
TABLE 39 - SOFTWARE RESET REGISTER (0x20 in
the direct accessed space)
Field
Bits
Length
Initial Value
SW_RESET
0
1
0
INIT_DONE
1
0
Reserved
7:2
6
0
The software reset bit is writable from the direct accessed memory space.
Writea“1”totheSW_RESETbittoinitiatethesoftwarereset.TheSW_RESET
bit will clear to a “0” after the chip has initialized itself. The INIT_DONE bit is set
toa“1”whentheinitializationfollowingresethascompleted.Thesoftwarereset
is the same as the hardware. The Reserved field must be set to 0.
TheInitialValuecolumninthisdocumentisthevalueoftheregisterafterreset
hascompleted.
SW_RESET SettingtheSW_RESETbitinitiatesasoftwareresetofthechip.
The SW_RESET bit is self-clearing.
0=No operation is performed
1=Initiate a software reset
INIT_DONE Status indication bit following a reset.
0=Chip has not completed initialization following reset
1= Chip has completed initialization following reset
SPI-4 status register (0x22 in the direct accessed
space)
相關(guān)PDF資料
PDF描述
IDT89H24NT24G2ZBHLG IC PCI SW 24LANE 24PORT 324BGA
IDT89HPES16NT2ZBBCG IC PCI SW 16LANE 2PORT 484-CABGA
IDT89HPES24NT3ZBBXG IC PCI SW 24LANE 3PORT 420-SBGA
IDT89HPES32T8ZHBXG IC PCI SW 32LANE 8PORT 500-SBGA
IDT89HPES8NT2ZBBCG IC PCI SW 8LANE 2PORT 324-CABGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT89H10T4BG2ZBBC 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
IDT89H10T4BG2ZBBC8 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
IDT89H10T4BG2ZBBCG 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT89H10T4BG2ZBBCG8 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
IDT89H10T4BG2ZBBCGI 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*