參數(shù)資料
型號(hào)： IDT88P8344BHI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 24/98頁(yè)
文件大?。?/td> 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8344BHI
30
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
4.2 SPI-4 to SPI-3 datapath and flow control
FourPacketFragmentProcessormodulesfromSPI4ingresstoSPI-3egress
are provided, all connected to one SPI-4 ingress interface.
PacketburstsfromtheSPI-4ingressarereceivedintotheSPI-4ingressport
buffers.Apacketfragmentprocessortransferscompletepacketburstsfromthe
SPI-4 ingress port buffers to memory segments previously reserved on a per-
LP basis in the buffer segment pool. The SPI-4 ingress port buffer watermarks
andtheper-LPfreebuffersegmentthresholdinformationiscombinedtoproduce
SPI-4 ingress FIFO status (per-LP starving, hungry, or satisfied) towards the
attachedSPI-4device.Per-LPbuffersegmentthresholdinformationisusedto
produce FIFO status information for the attached SPI-3 device. Packets or
packetfragmentsareforwardedtotheSPI-3interfacewhenapacketiscomplete
or a predefined number of bytes have been received. Packets or packet
fragments received on one SPI4 logical port are cross connected to an SPI3
logical port through an intermediate mapping to a Link identification, or LID. Its
modeofoperationissimilartotheSPI-3ingresstoSPI-4egresspacketfragment
processor, with the following differences:
1) The PFP4-3 data input has three sources, listed in descending priority:
SPI-4 buffers, redirect buffers, and insert buffers.
2) The PFP3-4 data output has only three destinations. There is no SPI-3
to SPI-4 redirect path.
Each SPI-3 interface feeds ingress buffer available or ingress buffer
unavailable status information to its packet fragment processor.
If the number of free segments available to a LP exceeds the starving
threshold,theSPI-4statusismovedtostarvingforthatLP.Ifthenumberoffree
segments available to a LP exceeds the hungry but not the starving threshold,
the SPI-4 status is moved to hungry for that LP. If the hungry threshold is not
exceeded, the SPI-4 FIFO status channel will indicate satisfied for that LP.
SPI-4 ingress to SPI-3 egress datapath
The following is a description of the path taken by a burst of data through the
device from the SPI-4 ingress to a SPI-3 egress.
Data enters on the SPI-4 ingress interface in bursts. Bursts are normally of
equallengthexceptthelastburstofapacketwhichmaybeshorter.Thecontrol
word is in-band with the data. Burst data enters a SPI-4 ingress buffer. SPI-4
LP address, error information, SOP, EOP are stored with the burst data. A SPI-
4 LP address is mapped to a Logical IDentifier (LID). The burst is stored in per
LID allocated buffer segments reserved from the buffer segment pool.
The appropriate SPI-3 egress control register (Table 80 - SPI-3 egress port
descriptor table (64 entries)) is consulted, and it determines to send this LID to
a prescribed SPI-3 egress port.
TheselectionofwhichLPistobetransmittednextisdependentonthestatus
of the LP and the availability of a complete fragment. Data is moved to the
appropriate SPI-3 egress buffer along with the LP address. SPI-3 LP address,
errorinformation,SOP,andEOPinformationisstoredwiththepacketfragment.
Next,dataistransmittedinpacketfragmentsovertheselectedSPI-3interface.
Figure 18. SPI-4 ingress to SPI-3 egress packet fragment processor
6370 drw37
FIFO Status
SPI4 Ingress
uP
capture
buffer
uP
insert
buffer
Associated
ingress PFP
SPI-3
redirect
buffers
buffer segment pool
SPI-3 egress port
buffers
SPI-4 ingress port
buffers
FIFO Status
Egress
SPI-3
相關(guān)PDF資料
PDF描述
IDT89H24NT24G2ZBHLG IC PCI SW 24LANE 24PORT 324BGA
IDT89HPES16NT2ZBBCG IC PCI SW 16LANE 2PORT 484-CABGA
IDT89HPES24NT3ZBBXG IC PCI SW 24LANE 3PORT 420-SBGA
IDT89HPES32T8ZHBXG IC PCI SW 32LANE 8PORT 500-SBGA
IDT89HPES8NT2ZBBCG IC PCI SW 8LANE 2PORT 324-CABGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT89H10T4BG2ZBBC 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
IDT89H10T4BG2ZBBC8 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
IDT89H10T4BG2ZBBCG 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT89H10T4BG2ZBBCG8 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
IDT89H10T4BG2ZBBCGI 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*