參數(shù)資料
型號： IDT88P8344BHI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 53/98頁
文件大?。?/td> 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8344BHI
57
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
TABLE 50 - SPI-3 GENERAL CONFIGURATION
REGISTER(REGISTER_OFFSET=0x00)
Field
Bits
Length
Initial Value
LINK
0
1
0b0
PACKET
1
0b1
SPI3_ENABLE
2
1
0b0
BUSWIDTH
3
1
0b0
EVEN_PARITY
4
1
0b0
PARITY_EN
5
1
0b1
Reserved
6
1
0b0
Reserved
7
1
0b0
WATERMARK
12:8
5
0x0F
Reserved
31:9
19
0x000
TABLE 49 - SPI-3 INGRESS LP TO LID MAP
Field
Bits
Length
Initial Value
LID
5:0
6
0x00
ENABLE
6
1
0b0
BIT_REVERSAL
7
1
0b0
There are 256 SPI-3 ingress Logical Port (LP) to Logical Identifier (LID)
registers, one per potential SPI-3 LP. Only 64 LPs per SPI-3 physical interface
can be enabled. An attempt to enable more than 64 LPs per SPI-3 physical
interface or to assign an identical LID to more than one LP will be discarded
and an error code will be returned. The ENABLE bit is used to enable SPI-
3 logical ports. All data from non-enabled SPI-logical ports is discarded and
aninactiveSPI-3logicalporteventisgenerated.Thiseventisdirectedtowards
the PMON & DIAG module. Disabled ports always generate available status.
The Table 49 - SPI-3 ingress LP to LID Map assigns a LID to a SPI-3 logical
port. LID mapping for 64 out of 256 SPI-3 logical ports is supported on each
SPI-3 physical port. LPs in the SPI Exchange are 8 bits wide[7:0] and range
from 0 to 255. An example of mapping SPI-3 physical interface “A”, LP 0x08
to LID 0x05, activating the LID, and not using bit reversal is outlined.
Perform an indirect write of 0x45 to register address Module_base 0x0000
+ Block_base 0x0000 + Register_offset 0x08 = 0x0008. Another example of
SPI-3 LP to LID mapping is to map SPI-3 “B”, LP 0xFF to LID 0x3F, write 0x7F
to register Module_base 0x2000 + Block_base 0x0000 + Register_offset
0xFF = 0x20FF.
The Initial Value column is the value of the register after reset.
LID
The LID programmed is associated to the LP with the same
number as the register address. Six bits support the 64 simultaneously active
LIDs per SPI-3 physical interface.
ENABLE
This bit is used to enable or disable the connection of this LP
to this LID.
0=LID disabled
1=LID enabled
BIT_REVERSAL This bit is used to reverse the bit ordering of each byte
of the SPI-3 interface on a per-LID basis.
0=Disable bit reversal for this LID
1=Enable bit reversal for this LID
9.3.2 Block base 0x0200 registers
SPI-3 general configuration register (Block_base
0x0200 + Register_offset 0x00)
There is one register for SPI-3 general configuration per SPI-3 interface.
Each register has read and write access. The address for module A is 0x0200,
moduleBis0x2200,moduleCis0x4200,andmoduleDis0x6200.Thebitfields
of the SPI-3 general configuration register are described in the following
paragraphs.
LINK A SPI-3 interface can be used either in Link or PHY modes. For
connectingtoatransmissionline-interfacePHY,programtheSPIExchangefor
Link mode. For connecting the SPI-3 interface to an NPU or other Link-mode
device, program the SPI-3 interface for PHY mode. Note that the four SPI-3
interfacescanbeindependentlyconfiguredintoeitherLinkorPHYmodes.The
SPI-3 ingress and egress of a given SPI-3 physical port will always be in the
samemode.
0= SPI-3 interface in PHY mode
1= SPI-3 interface in Link mode
PACKET
A SPI-3 interface can be used either in BYTE or PACKET
modes.ASPI-3interfaceactingasaLinklayerdevicecanpolltheattachedPHY
deviceforupto64LPsiftheattachedPHYdevicesupportsthepollinginterface.
When attached to a PHY device that only supports byte mode, the four direct
status indicators can be used. Note that the four SPI-3 interfaces can be
independently configured into either BYTE or PACKET modes. When the SPI
Exchange is in PHY mode, the PACKET bit is used to select either a polled or
direct status response to the attached Link device.
0 = BYTE mode with direct status indication for up to 4 LPs [3:0]
1= PACKET mode with polled status for up to 64 LPs
SPI3_ENABLE A SPI-3 interface can be enabled or disabled according
to the state programmed into this bit. A port should be disabled to save power
if it is not used.
0=SPI-3 Physical port disabled, outputs are in tristate
1=SPI-3 Physical port enabled
BUSWIDTH
A SPI-3 interface can be used as either a single 8-bit or 32-
bit interface, according to the needs of the attached device. The SPI-3 ingress
and egress of a given SPI-3 physical port will always be of the same bus width.
0=32 bit SPI-3 interface
1=8 bit SPI-3 interface
9.3.1 Block base 0x0000 registers
SPI-3 ingress LP to LID map (Block_base 0x0000 +
Register_offset 0x00 to 0xFF)
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