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參數(shù)資料
| 型號： | IDT88P8344BHI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 22/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 標準包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88P8344BHI |
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IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
SPI-3 ingress to SPI-4 egress flow control
For control information there are two separate cases to consider: The case
that the SPI-3 physical interface port is configured in Link mode, and the case
that the SPI-3 is configured in PHY mode. Note that since the SPI-3 physical
interfacesareconfiguredseparately,thedeviceisabletodealwiththecasethat
some of the LP fragments have been received on a Link layer device SPI-3
interfaceandsomehavebeenreceivedonaPHYlayerdeviceSPI-3interface.
For a device in Link mode the Link device can only control the flow of data
through the RENB signal. Two modes of operation are implemented and
configurable for flow control on this interface – either the data can be allowed
to flow freely into the device or the RENB signal will be asserted if a condition
arisesthatoneoftheLPsisunabletoreceiveanotherfragment.Thefirstofthese
modes is considered to have no Link layer device flow control, and the second
has Link layer device flow control.
For the no Link flow control mode, any data sent to an LP unable to receive
another fragment will cause an LP overflow.
For a device in Link mode the Link has complete knowledge of the fill level
ofthedatabuffersineachoftheLPsinthePHY.Thisknowledgeisattainedeither
through byte level polling or packet level polling.
Both in Link and PHY modes, the data is collected to buffer segments
associated with an LP. The SPI-4 PFP is updated with the number of free
segments available to the LP. The SPI-4 PFP determines which LP to service
based on two factors: whether the LP contains enough data for a burst, and the
starving / hungry / satisfied state of the LP. For details on the mapping of LPs
to LIDs, refer to Table 101 - SPI-4 egress LID to LP Map Block_base 0x0400
= Register_offset 0x00 - 0xFF.
SPI-3 ingress flow control registers
The following are implemented per SPI-3 interface, and there are four
instantiations per device.
Backpressure enable
Link mode only
Enables the assertion of the I_ENB pin when at least one active LID can not
acceptdata
Ifnotenabled,theI_ENBsignalwillneverbeassertedinLinkmode,possibly
leading to fragments being discarded.
SPI-4 egress flow control configurable parameters
All parameters as listed in SPI-4 implementation agreement:
CALENDAR_LEN: 4 to 1,024 in increments of 4
CALENDAR_M: 1 to 256 in increments of 1
MaxBurst1 (MaxBurst_S): 16 to 256 in increments of 16
MaxBurst2 (MaxBurst_H): 16 to 256 in increments of 16
Alpha: 1 to 256 in increments of 1
DATA_MAX_T: 1 to 4,294,967,040 in increments of 1
FIFO_MAX_T: 1 to 16,777,215 in increments of 1
SPI-4egressflowcontrolcalendarandshadowcalendar
256 entries
SPI-4 egress flow control multiple burst enable
Allows more than one burst to be sent to an LP. This feature was included
to increase throughput in systems with long latency between updates.
Figure 17. SPI-3 ingress to SPI-4 egress flow control path
…
JTAG
uproc
LID Counters Memory
4 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
Interface
Bloc
k
Chip Counters Memory
Interface
Bloc
k
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6370 drw12a
STATUS
DATA PATH
STATUS
ThediagrambelowshowstheSPI-3ingresstoSPI-4egressflowcontrolPath
through the IDT88P8344 device.
4
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