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參數(shù)資料
| 型號(hào)： | IDT88P8344BHI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 31/98頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88P8344BHI |
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37
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
4.4.4 SPI-4 ingress to microprocessor interface
datapath
The diagram below shows the datapath through the device from the SPI-4
interface to the microprocessor data capture interface.
The following is a description of the path taken by a burst of data through the
device.
Data enters on the SPI-4 interface in bursts. Bursts are normally of equal
length except the last burst of a packet which may be shorter. The control word
is in-band with the data. The burst data enters a SPI-4 ingress buffer. SPI-4 LP
address,errorinformation,SOP,andEOParestoredalongwiththeburstdata.
The SPI-4 LP address is mapped to a LID. Data is stored in per-LID allocated
buffer segments. The DIRECTION field of the SPI-3 egress port descriptor
(Block_base 0x1700 + Register_offset 0x00 - 0xFF) is used to send this LID
data to the microprocessor port. Data is moved to the capture buffer along with
the LP address, LID, error information, SOP, and EOP.
ThedataavailablebitissetbythePFP.Dataandcontrolinformationareread
from the capture buffer through the microprocessor interface.
Figure 29. SPI-4 ingress to microprocessor data capture interface path
…
JTAG
uproc
LID Counters Memory
4 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
Interface
Bloc
k
Chip Counters Memory
Interface
Bloc
k
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6370 drw17
Figure 28. Microprocessor data capture buffer
6370 drw28
flags
length
data[1]
data[2]
data[255]
lid
data[0]
SOP
EA
ED
PAR
EOP
not used
EA
ED
PAR
data parity error
address parity error
packet error
70
inser
tsequence
t
t+1
t+258
e
xtr
act
sequence
t
t+1
t+258
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