參數(shù)資料
型號(hào)： IDT88P8344BHI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 40/98頁(yè)
文件大?。?/td> 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8344BHI
45
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
For an ideal case, there is zero jitter on clock an data, zero skew, the clock
high and low level phase are symmetrical. For random input data on each lane,
the counters Cn=CNTn(t)+CNTn(t+1)+. . .+CNTn(t+T), where T is a time
window to do the statistics computation, will increment as follows:
Counter
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
8
C
9
Value
0
P
0
K
0
Where P and K are non-zero and need to be a large enough value mark
the transition position of a clock and define the position.
Software for implementing the Eye-Opening Check
IntheIDT88P8344,asetofdiagnosticregistersareprovidedforimplement-
ing an eye-opening check. The SPI-4 interface has 16 data lanes and one
control lane on ingress, 2 status lanes on egress, making a total of 19 lanes.
TheSPI-4ingressbitalignmentwindowregisterdefinesthewindowTstated
above, based on which the signal statistics are computed. It is recommended
to use the default value. The MEASURE_BUSY bit indicates the status of the
internalmeasurementoperation.
The SPI-4 ingress lane measure register selects the lane statistics counters
to be read, a write to this register triggers the eye-opening check process to the
selected lanes and the MEASURE_BUSY bit will be set accordingly indicating
themeasuringprocessisactive.TheMEASURE_BUSYbitisclearedinternally
which indicates that the measuring process is complete. The measured result
of counters C
0 through C9 will be available in the SPI-4 ingress bit alignment
counter registers.
Note that there is one SPI-4 ingress lane measure register and 19 SPI-4
ingress bit alignment counter registers.
The following pseudo code shows how to check the eye opening:
BecausetheSPI-4ingressbitalighnmentcounterregisterhasa10-bitwidth,
the maximum counter value is 0x3ff.
If the counter values of a lane are:
0, 0, 0x3ff, 0, 0, 0, 0, 0x3ff, 0, 0
The eye open is perfect; there is very good signal integrity on input signals
of the SPI-4 interface.
Ineachsamplepositionrepresentsa“tap”.Dependingonthedelayinalane,
even a small jitter value of 1ps on the lane or the clock, may cause eye closing
thatcanbedetectedbyobservingthecountervalues.Inanidealcasewithzero
delay, if the jitter on a data lane or clock is less than one tap interval (peak to
peak), the jitter will not be reflected in counters. While the eye open check can
indicate excessive jitter there are limitations in providing a accurate measure-
mentusingthismethod.
Theoretically as long as one tap accumulates enough non-zero samples for
each 2 bits within a clock cycle the sampled signal position will be correct and
the interface will function correctly. The more counters that have zero values,
the better the eye opening.
#define SPI-4_ingress_lane_measure_register 0x8801
/* register address in SPI exchange device*/
#define SPI-4_ingress_bit_alignment_counter_register(0) 0x8802
#define SPI-4_ingress_bit_alignment_counter_register(1) 0x8803
#define SPI-4_ingress_bit_alignment_counter_register(2) 0x8804
#define SPI-4_ingress_bit_alignment_counter_register(3) 0x8805
#define SPI-4_ingress_bit_alignment_counter_register(4) 0x8806
#define SPI-4_ingress_bit_alignment_counter_register(5) 0x8807
#define SPI-4_ingress_bit_alignment_counter_register(6) 0x8808
#define SPI-4_ingress_bit_alignment_counter_register(7) 0x8809
#define SPI-4_ingress_bit_alignment_counter_register(8) 0x880a
#define SPI-4_ingress_bit_alignment_counter_register(9) 0x880b
For lane=0 to K step 1
/*the number K depend on status mode: K=18 in LVDS status mode*/
{
/*
K=16otherwise */
write #lane, SPI-4_ingress_lane_measure_ register
wait until BUSY=0
/* BUSY: bit 8 of SPI-4_ingress_lane_measure_register, at address
0x8801*/
for i=0 to 9 step 1
{
read C(i), SPI-4_ingress_bit_alignment_counter_register(i)
}
print C(0), C(1), C(2), C(3), C(4), C(5), C(6), C(7), C(8), C(9)
}
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