參數(shù)資料
型號(hào): IDT88P8344BHI
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 78/98頁(yè)
文件大?。?/td> 0K
描述: IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝: 24
系列: *
其它名稱: 88P8344BHI
8
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
1. INTRODUCTION
The IDT88P8344 device is a quad SPI-3 to single SPI-4 exchange with
switchingcapabilitiesintendedforuseinVPNfirewallcards,Ethernettransport,
andmulti-serviceswitches.TheSPI-3andSPI-4interfacesaredefinedbythe
Optical Internetworking Forum (OIF).
Thedevicecanbeusedasanexchange,aswitch,oranaggregationdevice
betweennetworkprocessorunits,multi-gigabitframersandPHYs,andswitch
fabric interface devices.
Data Path Overview
Figure 2. Data Path Diagram shows an overview of the data path through
the device.
In normal operation, there are two paths through the IDT88P8344 device:
the quad SPI-3 ingress to SPI-4 egress path, and the SPI-4 ingress to quad
SPI-3 egress path. SPI-3 and SPI-4 burst sizes are separately configurable.
In the SPI-3 ingress to SPI-4 egress path, data enter in fragments on the
SPI-3 interface and are received by the SPI-3 interface block. The fragments
are mapped to a SPI-4 address and stored in memory allocated at the SPI-3
level until such a time that the SPI-3 to SPI-4 packet fragment processor
determines that they are to be transmitted on the SPI-4 interface. The data is
transferred in bursts, in line with the OIF SPI-4 implementation agreement, to
the SPI-4 interface block, and are transmitted on the SPI-4 interface.
In the SPI-4 ingress to SPI-3 egress path, data enter in bursts on the SPI-
4 interface and are received by the SPI-4 interface block. The SPI-4 address
is translated to a SPI-3 address, and the data contained in the bursts are stored
in memory allocated at the SPI-3 level until such a time that the SPI-4 to SPI-
3 packet fragment processor determines that they are to be transmitted on the
SPI-3 interface. The data is transferred in packet fragments, in line with the OIF
SPI-3 implementation agreement, to the SPI-3 interface block, and are trans-
mitted on the SPI-3 interface.
These and additional data paths are described in more detail in the data path
section of this document.
Figure 2. Data path diagram
SPI-3
SPI-3 ingress to SPI-4 egress
I/F
Memory
I/F
SPI-4
SPI-4 ingress to SPI-3 egress
6370 drw03
Multi-port
Ethernet
Transceiver
Multi-port
Ethernet
Transceiver
SPI-3
IDT88P8344
NPU
Co-Processor
SPI-3
SPI-4
SPI-3
Control
Processor
Memory
Clear Traffic
Secure Traffic
Additional
Co-Processor
or PHY
PCI
6370 drw02
TYPICAL APPLICATION
Exchange between secure traffic, clear traffic, 10G NPU and co-processor
Figure 1. Typical application: NPU, PHY, and co-processor
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