參數(shù)資料
型號： IDT72281L
廠商： Integrated Device Technology, Inc.
英文描述： CMOS SuperSync FIFO
中文描述： 先進先出的CMOS SuperSync
文件頁數(shù)： 9/26頁
文件大?。?/td> 277K
代理商： IDT72281L
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
Figure 4. Programmable Flag Offset Programming Sequence
Figure 3. Offset Register Location and Default Values
NOTES:
1. The programmng method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permtted regardless of which programmng method has been selected.
3. The programmng sequence applies to both IDT Standard and FWFT modes.
EMPTY OFFSET (LSB) REGISTER
8
7
0
IDT72281 (65,536 x 9
BIT)
FULL OFFSET (LSB) REGISTER
8
7
0
FULL OFFSET (MSB) REGISTER
8
7
0
D is LOW at Master Reset
7FH if
LD
FFH if
LD
is HIGH at Master Reset
DEFAULT VALUE
00H if
LD
is LOW at Master Reset
03H if
LD
is HIGH at Master Reset
DEFAULT VALUE
7FH if
LD
is LOW at Master Reset
FFH if
LD
is HIGH at Master Reset
EMPTY OFFSET (MSB) REGISTER
8
7
0
DEFAULT VALUE
00H if
LD
is LOW at Master Reset
03H if
LD
is HIGH at Master Reset
EMPTY OFFSET (LSB) REGISTER
8
7
0
IDT72291 (131,072 x 9
BIT)
FULL OFFSET (LSB) REGISTER
8
7
0
FULL OFFSET (MID-BYTE) REGISTER
8
7
0
DEFAULT VALUE
7FH if
LD
is LOW at Master Reset
FFH if
LD
is HIGH at Master Reset
DEFAULT VALUE
LD
7FH if
LD
is LOW at Master Reset
DEFAULT VALUE
00H if
LD
is LOW at Master Reset
03H if
LD
is HIGH at Master Reset
EMPTY OFFSET (MID-BYTE) REGISTER
8
7
0
DEFAULT VALUE
00H if
LD
is LOW at Master Reset
03H if
LD
is HIGH at Master Reset
8
1
0
8
0
1
DEFAULT
DEFAULT
EMPTY OFFSET
(MSB) REGISTER
FULL OFFSET
(MSB) REGISTER
4675 drw06
WCLK
RCLK
X
X
X
X
X
X
X
X
4675 drw07
LD
0
0
X
1
1
1
0
WEN
0
1
1
0
X
1
1
REN
1
0
1
X
0
1
1
X
SEN
1
1
1
X
X
X
0
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Memory
Read Memory
No Operation
Serial shift into registers:
32 bits for the IDT72281
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Empty Offset (MSB)
Full Offset (Mid-Byte)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Serial shift into registers:
34 bits for the IDT72291
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
No Operation
Write Memory
Read Memory
No Operation
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Full Offset (MSB)
IDT72281
IDT72291
相關(guān)PDF資料
PDF描述
IDT72281L10PF CMOS SuperSync FIFO
IDT72281L10PFI CMOS SuperSync FIFO
IDT72281L10TF CMOS SuperSync FIFO
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72281L10PF 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72281L10PF8 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72281L10PFG 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP
IDT72281L10PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 LP 10NS 64QFP
IDT72281L10TF 功能描述:IC FIFO 32768X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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